Offset cancel systems and methods for resolver-type sensors

Patent metadata

Field	Value
Publication number	US-11353337-B2
Application number	US-202117177346-A
Country	US
Kind code	B2
Filing date	Feb 17, 2021
Priority date	Nov 3, 2020
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

Implementations of a resolver sensor system may include a signal amplifier portion configured to be coupled to a magnetoresistive sensor coupled with a movable element where the signal amplifier portion configured to receive a sine signal and a cosine signal from the magnetoresistive sensor; and a sensor offset canceling portion coupled with a signal amplifier portion. The sensor offset canceling portion may be configured to generate a direct current offset correction signal to the signal amplifier portion which uses two or more amplifiers included in the signal amplifier portion to receive the sine signal and the cosine signal and to generate corresponding adjusted digital sine and cosine signals. The signal amplifier portion may be configured to provide the adjusted digital sine signal and the adjusted digital cosine signal to one of the servo signal processor or the system controller for use in determining a position of the movable element.

First claim

What is claimed is:

1. A resolver sensor system comprising:
a signal amplifier portion configured to be coupled to a magnetoresistive sensor, the magnetoresistive sensor configured to be coupled with a movable element, the signal amplifier portion configured to receive a sine signal and a cosine signal from the magnetoresistive sensor; and
a sensor offset canceling portion coupled with the signal amplifier portion and configured to be coupled with a system controller;
wherein the signal amplifier portion is configured to couple with a servo signal processor coupled with an actuator driver;
wherein the sensor offset canceling portion is configured to generate a direct current offset correction signal to the signal amplifier portion;
wherein the signal amplifier portion is configured to use two or more amplifiers comprised in the signal amplifier portion to receive the sine signal and the cosine signal and to generate a corresponding adjusted digital sine signal and a corresponding adjusted digital cosine signal; and
wherein the signal amplifier portion is configured to provide the adjusted digital sine signal and the adjusted digital cosine signal to one of the servo signal processor or the system controller for use in determining a position of the movable element.

2. The system of claim 1 , wherein the adjusted digital sine signal and the adjusted digital cosine signal were adjusted to remove a direct current offset present in the sine signal and a direct current offset present in the cosine signal, respectively.

3. The system of claim 2 , wherein the signal amplifier portion and the sensor offset canceling portion are configured to remove a direct current offset present in the sine signal and a direct current offset present in the cosine signal that includes one of asymmetry, amplitude fluctuation, or both asymmetry and amplitude fluctuation.

4. The system of claim 1 , wherein the signal amplifier portion further comprises a digital to analog converter coupled to a first one of the two or more amplifiers and an analog to digital converter coupled to a second one of the two or more amplifiers.

5. The system of claim 1 , wherein the sensor offset canceling portion further comprises:
a first noise reduction filter coupled to a first zero cross detector coupled with a first two AND gates, a first two multiplexers, a first two latches, and a first averaging module; and
a second noise reduction filter coupled to a second zero cross detector coupled with a second two AND gates, a second two multiplexers, a second two latches, and a second averaging module.

6. The system of claim 5 , wherein the first averaging module is configured to calculate a direct current offset for the sine signal and the second averaging module is configured to calculate a direct current offset for the cosine signal.

7. A sensor offset canceler for a resolver sensor system, the sensor offset canceler comprising:
a first noise reduction filter configured to receive a digital sine signal from a signal amplifier portion and generate a filtered digital sine signal;
a first zero cross detector configured to receive the filtered digital sine signal and output a rising zero cross point signal and a falling zero cross point signal;
a first two AND gates coupled with the first zero cross detector;
a first multiplexer and a first latch coupled with a first one of the first two AND gates;
a second multiplexer and a second latch coupled with a second one of the first two AND gates;
a first averaging module coupled with the first latch and with the second latch, the first averaging module configured to output a direct current offset correction for a cosine signal;
a second noise reduction filter configured to receive a digital cosine signal from a signal amplifier portion and generate a filtered digital cosine signal;
a second zero cross detector configured to receive the filtered digital cosine signal and output a rising zero cross point signal and a falling zero cross point signal;
a second two AND gates coupled with the second zero cross detector;
a third multiplexer and a third latch coupled with a first one of the second two AND gates;
a fourth multiplexer and a fourth latch coupled with a second one of the second two AND gates; and
a second averaging module coupled with the third latch and with the fourth latch, the second averaging module configured to output a direct current offset correction for a sine signal.

8. The canceler of claim 7 , wherein the first one of the first two AND gates is configured to receive a sine rising zero cross detection flag.

9. The canceler of claim 7 , wherein the second one of the first two AND gates is configured to receive a sine falling zero cross detection flag.

10. The canceler of claim 7 , wherein the first one of the second two AND gates is configured to receive a cosine rising zero cross detector flag.

11. The canceler of claim 7 , wherein the second one of the second two AND gates is configured to receive a cosine falling zero cross detector flag.

12. The canceler of claim 7 , wherein the first zero cross detector is configured to take a derivative of the filtered digital sine signal.

13. The canceler of claim 7 , wherein the second zero cross detector is configured to take a derivative of the filtered digital cosine signal.

14. A method of correcting direct current offset error for a resolver sensor system, the method comprising:
receiving a sine signal and a cosine signal from a resolver sensor at a signal amplifier portion;
amplifying the sine signal using a first one or more amplifiers;
amplifying the cosine signal using a second one or more amplifiers;
converting the sine signal to a digital sine signal using a first analog to digital converter;
converting the cosine signal to a digital cosine signal using a second analog to digital converter;
using a sensor offset canceling portion:
taking a derivative of the sine signal;
using a first zero cross detector, generating a sine rising zero cross signal and a sine falling zero cross signal using the derivative of the sine signal;
with a sine rising zero cross detection flag and a first AND gate, setting a state of a first sine rising latch;
with a sine falling zero cross detection flag and a second AND gate, setting a state of a second sine falling latch;
taking a derivative of the cosine signal;
using a second zero cross detector, generating a cosine rising zero cross signal and a cosine falling zero cross signal using the derivative of the cosine signal;
with a cosine rising zero cross detection flag and a third AND gate, setting a state of a third cosine rising latch;
with a cosine falling zero cross detection flag and a fourth AND gate, setting a state of a fourth cosine falling latch;
averaging outputs of the first sine rising latch and the second sine falling latch using a first averaging module and outputting an analog direct current cosine offset signal; and
averaging outputs of the third cosine rising latch and the fourth cosine falling latch using a second averaging module and outputting an analog direct current sine offset signal.

15. The method of claim 14 , further comprising:
generating a digital direct current cosine offset correction signal using a second digital to analog converter;
providing the digital direct current cosine offset correction signal to the second one or more amplifiers of the signal amplifier portion;
generating a digital direct current sine offset correction signal using a first digital to analog converter; and
providing the digital direct current sine offset correction signal t

Assignees

• Semiconductor Components Ind Llc

Inventors

• Takai Kazumasa

Classifications

• G01D5/2448

  Correction of gain, threshold, offset or phase control · CPC title

• G01D5/145 Primary

  influenced by the relative movement between the Hall device and magnetic fields (see G01R33/06) · CPC title

• G01D5/16 Primary

  by varying resistance · CPC title

• G01D5/24485

  using other sensors · CPC title