Memory device, layout, and method

Patent metadata

Field	Value
Publication number	US-12380957-B2
Application number	US-202117393121-A
Country	US
Kind code	B2
Filing date	Aug 3, 2021
Priority date	Apr 30, 2021
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

An integrated circuit (IC) device includes transistor and programmable structure regions. The transistor region includes a source structure configured to receive a reference voltage, a first portion of a drain structure, and a gate electrode positioned between the source structure and the first portion of the drain structure, and configured to receive an activation signal. The programmable structure region includes a second portion of the drain structure, a first signal line configured to receive an operational voltage, a second signal line, a gate via underlying and electrically connected to the first signal line, and a drain via positioned between and electrically connected to the second portion of the drain structure and the second signal line. Portions of the first signal line including a gate via location and the second signal line including a drain via location are positioned in parallel in a same metal layer of the IC device.

First claim

What is claimed is:

1. An integrated circuit (IC) device comprising:
a transistor region comprising:
a source structure configured to receive a reference voltage;
a first portion of a drain structure; and
a gate electrode positioned between the source structure and the first portion of the drain structure, and configured to receive an activation signal; and

a programmable structure region comprising:
a second portion of the drain structure;
a first signal line configured to receive an operational voltage;
a second signal line;
a gate via underlying and electrically connected to the first signal line; and
a drain via positioned between and electrically connected to the second portion of the drain structure and the second signal line,

wherein
a portion of the first signal line including a location of the gate via and a portion of the second signal line including a location of the drain via are positioned in parallel in a same metal layer of the IC device, and
a top portion of at least one of the gate via or the drain via extends between the first and second signal lines.

2. The IC device of claim 1 , wherein the same metal layer is a first metal layer of the IC device.

3. The IC device of claim 1 , wherein
the gate via is a first gate via of two gate vias underlying and electrically connected to the first signal line, and
each of the location of the first gate via and a location of a second gate via corresponds to a gate structure adjacent to the second portion of the drain structure.

4. The IC device of claim 1 , wherein
the gate via is a first gate via,
the drain structure is a first drain structure,
the drain via is a first drain via, and
the programmable structure region further comprises:
a third signal line adjacent to the first signal line and configured to receive the operational voltage;
a fourth signal line adjacent to the third signal line;
second and third gate vias underlying and electrically connected to the third signal line;
a second drain structure; and
a second drain via positioned between and electrically connected to the second drain structure and the fourth signal line.

5. The IC device of claim 4 , wherein the programmable structure region further comprises a fourth gate via underlying and electrically connected to the first signal line.

6. The IC device of claim 1 , wherein the transistor region comprises an n-type metal-oxide-semiconductor (NMOS) transistor comprising the source structure and the gate electrode.

7. The IC device of claim 1 , wherein
the gate electrode is a first gate electrode, and
the transistor region comprises:
a first transistor comprising the source structure, the first gate electrode, and a shared source/drain (S/D) structure; and
a second transistor comprising the shared S/D structure, the first portion of the drain structure, and a second gate electrode configured to receive a cascode bias voltage.

8. The IC device of claim 1 , wherein the programmable structure region comprises a gate electrode aligned with and electrically isolated from the gate electrode of the transistor region.

9. The IC device of claim 1 , wherein the programmable structure region comprises a metal segment in a metal layer above the same metal layer of the IC device, the first signal line being configured to receive the operational voltage from the metal segment.

10. The IC device of claim 1 , wherein
the portion of the first signal line including the location of the gate via and the portion of the second signal line including the location of the drain via extend in a first direction, and
the gate via and the drain via are offset from each other in the first direction.

11. A bit cell array comprising:
a first column comprising first and second transistor regions and a first programmable structure region between the first and second transistor regions; and
a second column comprising third and fourth transistor regions and a second programmable structure region between the third and fourth transistor regions, wherein
the first through fourth transistor regions comprise respective first through fourth drain structures,
each of the first and second programmable structure regions comprises:
first and second signal lines configured to receive respective first and second operational voltages;
first and second gate vias underlying and electrically connected to the first and second signal lines, respectively;
third and fourth signal lines;
a first drain via electrically connected to the third signal line and the corresponding first or second drain structure; and
a second drain via electrically connected to the fourth signal line and the corresponding third or fourth drain structure, wherein
a portion of the first signal line including a location of the first gate via and a portion of the third signal line including a location of the first drain via are arranged in parallel in a first metal layer, and
a portion of the second signal line including a location of the second gate via and a portion of the fourth signal line including a location of the second drain via are arranged in parallel in the first metal layer.

12. The bit cell array of claim 11 , wherein
each of the first through fourth transistor regions comprises a respective first through fourth transistor configured to selectively couple the corresponding first through fourth drain structure to a source structure configured to receive a reference voltage,
the first and third transistors comprise gates configured to receive a first activation signal, and
the second and fourth transistors comprise gates configured to receive a second activation signal.

13. The bit cell array of claim 12 , wherein each of the first through fourth transistors comprises an n-type metal-oxide-semiconductor (NMOS) transistor.

14. The bit cell array of claim 11 , wherein
each of the first through fourth transistor regions further comprises a respective fifth through eighth drain structure, and
each of the first and second programmable structure regions further comprises:
third and fourth gate vias underlying and electrically connected to the first and second signal lines, respectively;
a third drain via electrically connected to the third signal line and the corresponding fifth or sixth drain structure; and
a fourth drain via electrically connected to the fourth signal line and the corresponding seventh or eighth drain structure.

15. The bit cell array of claim 14 , wherein
the first and third gate vias are a first gate via pair adjacent to the third drain structure, and
the second and fourth gate vias are a second gate via pair adjacent to the second drain structure.

16. The bit cell array of claim 14 , wherein
the first and second gate vias are included in a first triangle pattern of gate vias adjacent to the first drain structure, and
the third and fourth gate vias are included in a second triangle pattern of gate vias adjacent to the fourth drain structure.

17. The bit cell array of claim 14 , wherein
the first and second gate vias are included in a first parallelogram pattern of gate vias adjacent to the first drain structure, and
the third and fourth gate vias are included in a second parallelogram pattern of gate vias adjacent to the fourth drain structure.

18. A method of manufacturing an integrated circuit (IC) device, the method comprising:
forming first and second drain structures on respective first and second active areas;
forming first and second drain vias on the respective first and second drain struct

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Hsiang-Wei
• Yang Andy
• Yang Yao-Jen

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B20/25 Primary

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title