Processor interrupt expansion feature

Patent metadata

Field	Value
Publication number	US-12379956-B2
Application number	US-202117521518-A
Country	US
Kind code	B2
Filing date	Nov 8, 2021
Priority date	Nov 8, 2021
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

An embodiment of an integrated circuit may comprise a processor with one or more cores and circuitry coupled to the one or more cores, the circuitry to control one or more interrupts based on an interrupt expansion data structure, and report information derived from the interrupt expansion data structure to a software interrupt handler. Other embodiments are disclosed and claimed.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a processor to be coupled to a memory, the processor comprising one or more cores and circuitry coupled to the one or more cores, the circuitry to:
receive a hardware interrupt comprising:
a first vector which is to indicate a class or interrupts; and
a first index which is to identify a bit location; and

based on the hardware interrupt:
access the memory, based on the first vector, to identify a first entry of one or more tables which are to comprise multiple entries which are each indexed based on a different respective vector, and which each indicate a respective one of multiple posted-interrupt data structures (PIDs) at the memory, wherein the multiple PIDs are each to comprise:
a respective bitmap comprising bits which each correspond to a different respective one of multiple interrupt sources; and
an identifier of a respective target processor of multiple processors;

identify a first posted-interrupt data structure (PID) of the multiple PIDs based on the first entry, wherein the first PID comprises a first bitmap, and wherein the first PID identifies a first target processor;
access a bit of the first bitmap based on the first index;
deliver an interrupt to a software interrupt handler; and
provide event information to the first target processor based on the bit of the first bitmap.

2. The integrated circuit of claim 1 , wherein a field of the first entry is to identify one of multiple available interrupt types comprising a virtual interrupt type and a user interrupt type.

3. The integrated circuit of claim 1 , wherein:
a field of the first entry is to identify a validity of the first entry; and
the circuitry is to access the bit of the first bitmap based on the validity.

4. The integrated circuit of claim 1 , wherein:
based on the hardware interrupt, the circuitry is to:
save a content of the first bitmap; and
clear the first bitmap; and

the event information indicates one or more delivered interrupts associated with the first vector.

5. The integrated circuit of claim 1 , wherein:
based on the hardware interrupt, the circuitry is to:
save the first index as the event information; and
selectively clear only the bit of the first bitmap.

6. A method at a processor, the method comprising:
receiving a hardware interrupt comprising:
a first vector which indicates a class or interrupts; and
a first index which identifies a bit location; and

based on the hardware interrupt:
accessing a memory coupled to the processor, based on the first vector, to identify a first entry of one or more tables comprising multiple entries which are each indexed based on a different respective vector, and which each indicate a respective one of multiple posted-interrupt data structures (PIDs) at the memory, wherein the multiple PIDs each comprise:
a respective bitmap comprising bits which each correspond to a different respective one of multiple interrupt sources; and
an identifier of a respective target processor of multiple processors;

identifying a first posted-interrupt data structure (PID) of the multiple PIDs based on the first entry, wherein the first PID comprises a first bitmap, and wherein the first PID identifies a first target processor;
accessing a bit of the first bitmap based on the first index;
delivering an interrupt to a software interrupt handler; and
providing event information to the first target processor based on the bit of the first bitmap.

7. The method of claim 6 , wherein a field of the first entry identifies one of multiple available interrupt types comprising a virtual interrupt type and a user interrupt type.

8. The method of claim 7 , wherein:
a field of the first entry identifies a validity of the first entry; and
the bit of the first bitmap is accessed based on the validity.

9. The method of claim 8 , wherein:
the method further comprises:
saving a content of the first bitmap; and
clearing the first bitmap; and

the event information indicates one or more delivered interrupts associated with the first vector.

10. The method of claim 8 , further comprising:
based on the hardware interrupt:
saving the first index as the event information; and
selectively clearing only the bit of the first bitmap.

11. An apparatus, comprising:
memory to store:
multiple posted-interrupt data structures (PIDs) which are each to comprise:
a respective bitmap comprising bits which each correspond to a different respective one of multiple interrupt sources; and
an identifier of a respective target processor of multiple processors; and

one or more tables comprising multiple entries which are each indexed based on a different respective vector, and which each indicate a respective one of the multiple PIDs; and

a processor coupled to the memory, the processor including one or more cores and circuitry coupled to the one or more cores to:
receive a hardware interrupt comprising:
a first vector which is to indicate a class or interrupts; and
a first index which is to identify a bit location; and

based on the hardware interrupt:
access the memory, based on the first vector, to identify a first entry of the one or more tables;
identify a first posted-interrupt data structure (PID) of the multiple PIDs based on the first entry, wherein the first PID comprises a first bitmap, and wherein the first PID identifies a first target processor;
access a bit of the first bitmap based on the first index;
deliver an interrupt to a software interrupt handler; and
provide event information to the first target processor based on the bit of the first bitmap.

12. The apparatus of claim 11 , wherein a field of the first entry is to identify one of multiple available interrupt types comprising a virtual interrupt type and a user interrupt type.

13. The apparatus of claim 11 , wherein:
a field of the first entry is to identify a validity of the first entry; and
the circuitry is to access the bit of the first bitmap based on the validity.

14. The apparatus of claim 11 , wherein:
based on the hardware interrupt, the circuitry is to:
save a content of the first bitmap; and
clear the first bitmap; and

the event information indicates one or more delivered interrupts associated with the first vector.

15. The apparatus of claim 11 , wherein:
based on the hardware interrupt, the circuitry is to:
save the first index as the event information; and
selectively clear only the bit of the first bitmap.

Assignees

• Intel Corp

Inventors

• Neiger Gilbert
• Sankaran Rajesh

Classifications

• G06F9/461

  Saving or restoring of program or task context · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/327

  for interrupts · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title