Passivation layers for thin film transistors

Patent metadata

Field	Value
Publication number	US-12376342-B2
Application number	US-202418444520-A
Country	US
Kind code	B2
Filing date	Feb 16, 2024
Priority date	Jun 26, 2020
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

First claim

What is claimed is:

1. A transistor structure, comprising:
a gate electrode;
a gate insulator over the gate electrode;
a channel material over the gate insulator, wherein the channel material comprises a first metal and oxygen;
a material layer in contact with the channel material, opposite the gate insulator, wherein the material layer comprises a second metal absent from the channel material; and
source and drain contacts coupled with the channel material.

2. The transistor structure of claim 1 , wherein the channel material has n-type conductivity and the material layer has p-type conductivity.

3. The transistor structure of claim 1 , wherein the channel material has p-type conductivity and the material layer has n-type conductivity.

4. The transistor structure of claim 1 , wherein the material layer is a first material layer, and further comprising:
a second material layer in contact with the first material layer, wherein the second material layer comprises oxygen and at least one of Al, Y, or Hf or comprises nitrogen and Al or Si; and
a dielectric material layer over the second material layer, wherein the dielectric material layer has a different composition that the second material layer.

5. The transistor structure of claim 1 , wherein the first metal is In, Zn, Ga, Al, Sn, Mg, or Hf.

6. The transistor structure of claim 5 , wherein the channel material is InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, or InMgZnO.

7. The transistor structure of claim 5 , wherein the second metal is Cu, Nb, Ni, Co, Sn, Ag, Al, Sc, Sr, La, Na, K, Rb, Fe, Zn, or Rh.

8. The transistor structure of claim 7 , wherein the material layer is CuO x , NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, or ZnRh2O4.

9. The transistor structure of claim 1 , wherein the first metal is Cu, Nb, Ni, Co, Sn, Ag, Al, Sc, Sr, La, Na, K, Rb, Fe, Zn, or Rh.

10. The transistor structure of claim 9 , wherein the channel material is CuO x , NbO, NiO, CoO, SnO, Cu20, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, or ZnRh2O4.

11. The transistor structure of claim 9 , wherein the second metal is In, Zn, Ga, Al, Sn, Mg, or Hf.

12. The transistor structure of claim 11 , wherein the material layer is InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, or InMgZnO.

13. A system comprising:
a transistor structure, comprising:
a gate electrode;
a gate insulator over the gate electrode;
a channel material over the gate insulator, wherein the channel material comprises a first metal and oxygen;
a multi-layer material stack over the channel material, opposite the gate insulator;
a dielectric material over the multi-layer material stack; and
source and drain contacts coupled with the channel material,
wherein the multi-layer material stack comprises:
a first material layer comprising a second metal absent from the channel material; and
a second material layer between the first material layer and the dielectric material, wherein the second material layer has a different composition than the dielectric material; and

a memory element coupled with the transistor structure.

14. The system of claim 13 , wherein the memory element is a magnetic tunnel junction device or a resistive random-access memory device.

15. The system of claim 13 , wherein the channel material has a first conductivity type and the first material layer has a second conductivity type, complementary to the first conductivity type.

16. The system of claim 13 , wherein the second material layer comprises oxygen and at least one of Al, Y, Hf or comprises nitrogen and Al or Si, and wherein the dielectric material comprises Si and oxygen.

17. An integrated circuit (IC) comprising a thin film transistor, wherein the thin film transistor comprises:
a gate insulator over a gate electrode;
a channel material over the gate insulator, wherein the channel material comprises a first metal and oxygen;
a multi-layer material stack over the channel material, opposite the gate insulator;
a dielectric material over the multi-layer material stack; and
source and drain contacts coupled with the channel material,
wherein the multi-layer material stack comprises:
a first material layer comprising a second metal absent from the channel material; and
a second material layer between the first material layer and the dielectric material, wherein the second material layer has a different composition than the dielectric material.

18. The IC of claim 17 , wherein one of the first or second metals is In, Zn, Ga, Al, Sn, Mg, or Hf and another of the first or second metals is Cu, Nb, Ni, Co, Sn, Ag, Al, Sc, Sr, La, Na, K, Rb, Fe, Zn, or Rh.

19. The IC of claim 18 , wherein the second material layer comprises oxygen and at least one of Al, Y, or Hf or wherein the second material layer comprises nitrogen and Al or Si.

20. The IC of claim 19 , wherein the dielectric material comprises Si and oxygen.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek A
• Sen Gupta Arnab
• Lajoie Travis W
• Atanasov Sarah
• Ku Chieh-Jen
• Sell Bernhard
• Sato Noriyuki
• Le Van
• Metz Matthew
• Yoo Hui Jae
• Wang Pei-Hua

Classifications

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10B63/30

  comprising selection components having three or more electrodes, e.g. transistors · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title