Radio-frequency switch having redistribution layer inductance

Patent metadata

Field	Value
Publication number	US-12376341-B2
Application number	US-202217851169-A
Country	US
Kind code	B2
Filing date	Jun 28, 2022
Priority date	Jun 29, 2021
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

In some embodiments, a semiconductor chip device can include a semiconductor substrate having a switching circuit with a first node, and a plurality of layers configured to support the semiconductor substrate and to provide electrical connections for the switching circuit between a second node connectable to a location external to the semiconductor chip and the first node. The plurality of layers can include a redistribution layer, and a signal path can be implemented as a part of the redistribution layer. The signal path can have a first end electrically connected to the first node and a second end electrically connected to the second node, and be configured to provide a selected inductance.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a semiconductor substrate having a switching circuit with a first node;
a plurality of layers configured to support the semiconductor substrate and to provide electrical connections for the switching circuit between a second node connectable to a location external to the semiconductor chip and the first node, the plurality of layers including a redistribution layer that is a layer positioned furthest away from the semiconductor substrate among the plurality of layers; and
a signal path implemented as a part of the redistribution layer, the signal path having a first end electrically connected to the first node and a second end electrically connected to the second node, the signal path configured to provide a selected inductance that compensates for some or all of parasitic capacitance associated with the switching circuit.

2. The semiconductor chip of claim 1 wherein the semiconductor chip is implemented as a flip chip device.

3. The semiconductor chip of claim 1 wherein the semiconductor substrate includes a silicon-on-insulator substrate.

4. The semiconductor chip of claim 3 wherein the switching circuit includes a plurality of switching transistors, such that at least some of the parasitic capacitance results from one or more switching transistors in an OFF state.

5. The semiconductor chip of claim 1 wherein the selected inductance compensating for the parasitic capacitance results in a reduced insertion loss associated with the switching circuit.

6. The semiconductor chip of claim 1 wherein the second node is configured to receive an amplified signal from a power amplifier.

7. The semiconductor chip of claim 1 wherein the first node is configured as a pole connectable to one or more of a plurality of throws of the switching circuit.

8. A semiconductor chip comprising:
a semiconductor substrate having a switching circuit with a first node;
a plurality of layers configured to support the semiconductor substrate and to provide electrical connections for the switching circuit between a second node connectable to a location external to the semiconductor chip and the first node, the plurality of layers including a redistribution layer; and
a signal path implemented as a part of the redistribution layer, the signal path having a first end electrically connected to the first node and a second end electrically connected to the second node, the signal path configured to provide a selected inductance that compensates for some or all of parasitic capacitance associated with the switching circuit, the signal path including a copper trace having thickness and width values and extends in partial or full winding(s) to provide the selected inductance and a desired Q value.

9. The semiconductor chip of claim 8 wherein the selected inductance is in a range of 0.1 nH to 10 nH, and the desired Q value is greater than 20.

10. The semiconductor chip of claim 9 wherein the selected inductance in a range of 0.8 nH to 1.2 nH, and the desire Q value is at least 25 at a frequency in a range of 2 GHz to 3 GHZ.

11. The semiconductor chip of claim 9 wherein the copper trace extends in approximately one winding.

12. A method for manufacturing a semiconductor chip device, the method comprising:
forming a plurality of layers including a redistribution layer, the forming of the redistribution layer including implementing a signal path as part of the redistribution layer such that the signal path provides a selected inductance with a first end electrically connected to a first node and a second end electrically connected to a second node; and
coupling a semiconductor substrate with a switching circuit to the plurality of layers, such that the first node is electrically connected to the switching circuit and the second node is connectable to a location external to the semiconductor chip device, such that the redistribution layer is a layer positioned furthest away from the semiconductor substrate among the plurality of layers, and the selected inductance compensates for some or all of parasitic capacitance associated with the switching circuit.

13. A packaged module comprising:
a packaging substrate; and
a semiconductor chip mounted on the packaging substrate, the semiconductor chip including a semiconductor substrate having a switching circuit with a first node, and a plurality of layers configured to support the semiconductor substrate and to provide electrical connections for the switching circuit between a second node connectable to a location external to the semiconductor chip and the first node, the plurality of layers including a redistribution layer that is a layer positioned furthest away from the semiconductor substrate among the plurality of layers, the semiconductor chip further including a signal path implemented as a part of the redistribution layer, the signal path having a first end electrically connected to the first node and a second end electrically connected to the second node, the signal path configured to provide a selected inductance that compensates for some or all of parasitic capacitance associated with the switching circuit.

14. The packaged module of claim 13 wherein the semiconductor chip is implemented as a flip chip device.

Assignees

• Skyworks Solutions Inc

Inventors

• Ye Peihua
• Blin Guillaume Alexandre
• Obkircher Thomas

Classifications

• H10W20/497 Primary

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W44/20 Primary

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H03D7/1441

  using field-effect transistors (H03D7/145 takes precedence) · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title