Semiconductor memory device and method for manufacturing semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12376302-B2
Application number	US-202217806111-A
Country	US
Kind code	B2
Filing date	Jun 9, 2022
Priority date	Mar 18, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A semiconductor memory device of an embodiment includes: a semiconductor layer extending in a first direction; a gate electrode layer containing at least one element selected from a group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), and cobalt (Co); a first insulating layer provided between the semiconductor layer and the gate electrode layer; a charge storage layer provided between the first insulating layer and the gate electrode layer; a second insulating layer provided between the charge storage layer and the gate electrode layer; a third insulating layer provided between the second insulating layer and the gate electrode layer; and a metal oxide layer provided between the third insulating layer and the gate electrode layer and containing at least one first metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta).

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a semiconductor layer extending in a first direction;
a first gate electrode layer containing at least one element selected from a group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), and cobalt (Co);
a first insulating layer provided between the semiconductor layer and the first gate electrode layer;
a charge storage layer provided between the first insulating layer and the first gate electrode layer, the charge storage layer extending in the first direction;
a second insulating layer provided between the charge storage layer and the first gate electrode layer, the second insulating layer extending in the first direction;
a third insulating layer including a first portion, a second portion, and a third portion, the first portion being provided between the second insulating layer and the first gate electrode layer; and
a metal oxide layer provided between the third insulating layer and the gate electrode layer and containing a first metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta),
wherein the second portion and the third portion face in the first direction, and the first gate electrode layer is provided between the second portion and the third portion in the first direction.

2. The semiconductor memory device according to claim 1 , further comprising a metal nitride layer provided between the metal oxide layer and the third insulating layer and containing a second metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta).

3. The semiconductor memory device according to claim 1 , further comprising a metal nitride layer provided between the metal oxide layer and the gate electrode layer and containing at least one second metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta).

4. The semiconductor memory device according to claim 2 , wherein the first metal element and the second metal element are a same element.

5. The semiconductor memory device according to claim 3 , wherein the first metal element and the second metal element are a same element.

6. The semiconductor memory device according to claim 2 , wherein a thickness of the metal nitride layer is thicker than a thickness of the metal oxide layer.

7. The semiconductor memory device according to claim 1 , wherein the second insulating layer contains a first element and oxygen (O), and the third insulating layer contains a second element different from the first element and oxygen (O).

8. The semiconductor memory device according to claim 7 , wherein the first element is silicon (Si), and the second element is aluminum (Al).

9. The semiconductor memory device according to claim 1 , wherein the at least one element is molybdenum (Mo).

10. The semiconductor memory device according to claim 2 , wherein the first metal element and the second metal element are titanium (Ti).

11. A semiconductor memory device, comprising:
a semiconductor layer extending in a first direction;
a first gate electrode layer containing molybdenum (Mo);
a first insulating layer provided between the semiconductor layer and the gate electrode layer;
a charge storage layer provided between the first insulating layer and the first gate electrode layer, the charge storage layer extending in the first direction;
a second insulating layer provided between the charge storage layer and the first gate electrode layer and containing silicon (Si) and oxygen (O), the second insulating layer extending in the first direction; and
a third insulating layer including a first portion, a second portion, and a third portion, the first portion being provided between the second insulating layer and the first gate electrode layer and containing aluminum (Al), oxygen (O), and nitrogen (N),
wherein the second portion and the third portion face in the first direction, and the first gate electrode layer is provided between the second portion and the third portion in the first direction.

12. The semiconductor memory device according to claim 11 , wherein the second insulating layer contains nitrogen (N).

13. The semiconductor memory device according to claim 1 , further comprising:
a second gate electrode layer provided above the first gate electrode layer, the second gate electrode layer containing the at least one element; and
a fourth insulating layer provided between the first gate electrode layer and the second gate electrode layer,
wherein the charge storage layer is provided between the second insulating layer and the second gate electrode layer, and the second insulating layer is provided between the charge storage layer and the second gate electrode layer.

14. The semiconductor memory device according to claim 11 , further comprising:
a second gate electrode layer provided above the first gate electrode layer, the second gate electrode layer containing the at least one element; and
a fourth insulating layer provided between the first gate electrode layer and the second gate electrode layer,
wherein the charge storage layer is provided between the second insulating layer and the second gate electrode layer, and the second insulating layer is provided between the charge storage layer and the second gate electrode layer.

Assignees

• Kioxia Corp

Inventors

• Ohsawa Saho
• Fujii Kenichi
• Fukushima Takashi
• Ohtori Hiroyuki
• Katou Kaihei
• Kato Masaki
• SAWABE Ryosuke
• Sakai Yuji

Classifications

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title