Memory device

Patent metadata

Field	Value
Publication number	US-12376285-B2
Application number	US-202218054986-A
Country	US
Kind code	B2
Filing date	Nov 14, 2022
Priority date	Dec 8, 2021
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.

First claim

What is claimed is:

1. A memory device comprising:
a substrate;
a fin structure on the substrate;
a gate structure on the fin structure;
a first source/drain at one end of the fin structure; and
a second source/drain at another end of the fin structure,
wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer that are sequentially stacked on the fin structure,
the first source/drain has dopants of a first conductivity-type incorporated therein, and
the second source/drain has dopants of a second conductivity-type incorporated therein, the second conductivity-type different from the first conductivity-type.

2. The memory device of claim 1 , wherein the fin structure includes at least one of single crystal silicon, polysilicon, oxide semiconductor, germanium, silicon-germanium, or transition metal dichalcogenide (TMDC).

3. The memory device of claim 1 , wherein the trap layer includes at least one of silicon nitride, hafnium oxide, or silicon oxynitride.

4. The memory device of claim 1 , wherein the blocking layer includes at least one of silicon oxide, aluminum oxide, or hexagonal boron nitride.

5. The memory device of claim 1 , wherein the gate electrode layer includes at least one of tungsten, titanium nitride, titanium, ruthenium, molybdenum, nickel, or grapheme.

6. The memory device of claim 1 , wherein the first source/drain includes at least one of single crystal silicon, polysilicon, oxide semiconductor, germanium, silicon-germanium, or transition metal dichalcogenide (TMDC).

7. The memory device of claim 1 , wherein the second source/drain includes at least one of single crystal silicon, polysilicon, oxide semiconductor, germanium, silicon-germanium, or transition metal dichalcogenide (TMDC).

8. The memory device of claim 1 , wherein the substrate and the fin structure include a same material or same materials.

9. The memory device of claim 8 , wherein the substrate and the fin structure both include silicon.

10. The memory device of claim 1 , wherein the fin structure directly contacts the trap layer.

11. A memory device comprising:
a substrate;
a first fin structure on the substrate;
a second fin structure separated from the first fin structure in a first horizontal direction;
a first source/drain located at one end of the first fin structure and having dopants of a first conductivity-type incorporated therein;
a second source/drain located at another end of the first fin structure and having dopants of a second conductivity-type incorporated therein, the second conductivity-type different from the first conductivity-type;
a third source/drain located at one end of the second fin structure and having dopants of the first conductivity-type incorporated therein;
a fourth source/drain located at another end of the second fin structure and having dopants of the second conductivity-type incorporated therein;
a first gate structure including a first trap layer, a first blocking layer, and a first gate electrode layer sequentially stacked on the first fin structure;
a second gate structure including a second trap layer, a second blocking layer, and a second gate electrode layer sequentially stacked on the second fin structure;
a first bit line connected to the first source/drain and the third source/drain; and
a first source line connected to the second source/drain and the fourth source/drain.

12. The memory device of claim 11 , wherein the first bit line and the first source line extend in the first horizontal direction.

13. The memory device of claim 11 , wherein the first gate structure and the second gate structure extend in a second horizontal direction.

14. The memory device of claim 11 , further comprising:
a third fin structure separated from the first fin structure in a second horizontal direction;
a fifth source/drain at one end of the third fin structure and having dopants of the first conductivity-type incorporated therein; and
a sixth source/drain at another end of the third fin structure and having dopants of the second conductivity-type incorporated therein,
wherein the first gate structure extends on the third fin structure.

15. The memory device of claim 14 , further comprising:
a second bit line connected to the fifth source/drain and extending in the first horizontal direction; and
a second source line connected to the sixth source/drain and extending in the first horizontal direction.

16. The memory device of claim 15 , further comprising:
a fourth fin structure separated from the third fin structure in the first horizontal direction and separated from the second fin structure in the second horizontal direction;
a seventh source/drain at one end of the fourth fin structure and having dopants of the first conductivity-type incorporated therein; and
an eighth source/drain at the other end of the fourth fin structure and having dopants of the second conductivity-type incorporated therein,
wherein the second bit line is connected to the seventh source/drain, and
the second source line is connected to the eighth source/drain.

17. The memory device of claim 11 , further comprising:
a first connection structure connecting the first source/drain to the first bit line;
a second connection structure connecting the second source/drain to the first source line;
a third connection structure connecting the third source/drain to the first bit line; and
a fourth connection structure connecting the fourth source/drain to the first source line.

18. The memory device of claim 11 , wherein the first bit line is separated from the first source line in a second horizontal direction.

19. The memory device of claim 11 , wherein the first bit line and the first source line are separated from the substrate.

20. A memory device comprising:
a silicon substrate;
a silicon fin structure on the silicon substrate;
a first source/drain at one end of the silicon fin structure and having dopants of a first conductivity-type incorporated therein;
a second source/drain at another end of the silicon fin structure and having dopants of a second conductivity-type incorporated therein, the second conductivity-type different from the first conductivity-type;
a nitride layer on the silicon fin structure;
an oxide layer on the nitride layer; and
a gate electrode layer on the oxide layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyuncheol
• Kim Yongseok
• Lee Kyunghwan
• Lee Minjun
• Ha Daewon

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/694 Primary

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D12/211

  Gated diodes · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title