Hybrid rate interface to reduce power consumption and area in high-speed DACs and digital transmitters

Patent metadata

Field	Value
Publication number	US-12375102-B2
Application number	US-202318133403-A
Country	US
Kind code	B2
Filing date	Apr 11, 2023
Priority date	Apr 11, 2023
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

An system includes a port to receive a number of bits at a first frequency. One or more cells generate a signal for a channel with a channel frequency that is N times greater than the first frequency. The cells transmit at a second frequency that is M times greater than the first frequency but is smaller than the channel frequency. Interface links are coupled between a portion of the input bits of the port and the one or more cells and the portion of the input bits is encoded by thermometer coded T bits such that each one of the T bits is encoded by M repeated parallel bits having a value of a respective T bit. Each interface link includes M interface lines between each T bit and each first cell, and M is smaller than N to reduce the number of interface lines for the T bits.

First claim

What is claimed is:

1. A system, comprising:
a port configured to receive input bits at a first frequency;
one or more first cells configured to transmit at a second frequency that is N times greater than the first frequency;
one or more first interface links coupled between a first portion of the input bits and the one or more first cells, wherein each input bit of the first portion is encoded by N repeated parallel bits with a value of a respective input bit and each first interface link comprises N parallel interface lines between the N repeated parallel bits of each input bit of the first portion and each first cell;
one or more second cells configured to transmit at a third frequency that is M times greater than the first frequency; and
one or more second interface links coupled between a second portion of the input bits and the one or more second cells, wherein the second portion of the input bits is encoded by thermometer coded T bits, wherein each one of the T bits is encoded by M repeated parallel bits, and wherein each second interface link comprises M parallel interface lines between the M repeated parallel bits of each T bit and each second cell, wherein M is less than N and greater or equal to one, to reduce a number of interface lines per bit for the second portion of the input bits compared to the first portion of the input bits.

2. The system of claim 1 , wherein N is equal to 16, wherein the first portion of the input bits is binary coded such that each bit is encoded by 16 repeated parallel bits, wherein each first interface link is coupled between the 16 repeated parallel bits and each first cell.

3. The system of claim 1 , wherein the input bits comprises 13 bits, the first portion comprises 7 bits, and the second portion comprises 6 bits.

4. The system of claim 1 , wherein the thermometer coded T bits at most comprises one transition between the T bits, and wherein the second portion comprises 6 bits and the thermometer coded T bits are 64.

5. The system of claim 1 , wherein each first cell comprises a serializer configured to serialize N repeated parallel bits.

6. The system of claim 5 , wherein each first cell comprises a signal-generator configured to generate an analog signal from the serialized N repeated parallel bits at the second frequency.

7. The system of claim 1 , wherein the first portion comprises least significant input bits of the port, and the second portion comprises most significant input bits of the port.

8. A system, comprising:
a port comprising a number of input bits, wherein the port is configured to receive the input bits at a first frequency;
one or more first cells configured to generate a signal for a channel at a channel frequency that is N times greater than the first frequency, wherein N is larger than one, wherein the one or more first cells are configured to transmit at a second frequency that is M times greater than the first frequency and the second frequency is smaller than the channel frequency; and
one or more first interface links coupled between a first portion of the input bits of the port and the one or more first cells, wherein the first portion of the input bits is encoded by thermometer coded T bits, wherein each one of the T bits is encoded by M repeated parallel bits with a value of a respective T bit, wherein each first interface link comprises M interface lines between each T bit and each first cell, and wherein M is smaller than N to reduce the number of interface lines for the T bits.

9. The system of claim 8 , wherein the first frequency is 1 GHz, the channel frequency is 16 GHz, and the second frequency is either 4 GHz or 8 GHz, and wherein each first interface link comprises either 4 or 8 interface lines.

10. The system of claim 8 , further comprising:
one or more second cells configured to transmit at the channel frequency; and
one or more second interface links coupled between two or more bits of the input bits of the port and the one or more second cells, wherein each bit of the two or more bits is a binary coded bit and is encoded by N repeated parallel bits with a value of a respective input bit and each second interface link comprises N interface lines between the N repeated parallel bits of each binary coded bit and each second cell.

11. The system of claim 10 , wherein the input bits comprises 13 bits, the first portion comprises 5 bits, and the two or more bits comprises 8 bits.

12. The system of claim 8 , wherein each first cell comprises a signal-generator configured to generate an analog signal from a serialized M parallel bits at the second frequency.

13. The system of claim 8 , wherein the first portion comprises most significant bits of the input bits.

14. The system of claim 8 , wherein T equals 64 and M equals one.

15. A system, comprising:
a port comprising a first binary coded bit and a second thermometer coded bit, wherein the port is configured to receive the first binary coded bit and the second thermometer coded bit at a first frequency;
a first cell configured to transmit at a second frequency that is N times greater than the first frequency, wherein N is greater than one;
a first interface link coupled between the first binary coded bit and the first cell, wherein the first binary coded bit is encoded by N repeated parallel bits with a value of a respective input bit and the first interface link comprises N interface lines between the first binary coded bit and the first cell;
a second cell configured to transmit at a third frequency that is M times greater than the first frequency, wherein M is larger or equal to one; and
a second interface link coupled between the second thermometer coded bit and the second cell, wherein the second thermometer coded bit is encoded by thermometer coded T bits, wherein each one of the T bits is encoded by M repeated parallel bits with a value of the second thermometer coded bit, wherein the second interface link comprises M interface lines between the M repeated parallel bits and the second cell, and wherein M is smaller than N to reduce an area used by the second interface link compared to the first interface link.

16. The system of claim 15 , further comprising:
two or more thermometer coded bits including the second thermometer coded bit, wherein a number of T bits is 2 to a power of a total number of thermometer coded bits.

17. The system of claim 16 , wherein values of the T bits are down sampled by N over M.

18. The system of claim 16 , further comprising:
two or more binary coded bits including the first binary coded bit, wherein a total number of binary coded bits and thermometer coded bits is 13.

19. The system of claim 18 , wherein N is 16 and M is 2, and wherein the system receives the two or more binary coded bits and the two or more thermometer coded bits at 1 GHz, the binary coded bits are transmitted at 16 GHz, and the thermometer coded bits are transmitted at 2 GHz.

20. The system of claim 18 , wherein the two or more binary coded bits are transmitted at a channel frequency and the T bits are transmitted at N over M times lower than the channel frequency, and wherein for the T bits, N over M times fewer interface lines is used and N over M times less power and area is used compared to the two or more binary coded bits.

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Mikhemar Mohyee
• Lin Alvin Lai
• Blanksby Andrew J
• Sowlati Tirdad
• Behzad Arya

Classifications

• H03M7/165

  Conversion to or from thermometric code · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title

• H04B1/04

  Circuits · CPC title

• H03K19/017509

  Interface arrangements · CPC title