Method for manufacturing electronic device

Patent metadata

Field	Value
Publication number	US-12374560-B2
Application number	US-202217969703-A
Country	US
Kind code	B2
Filing date	Oct 20, 2022
Priority date	Jul 29, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

The present disclosure discloses a manufacturing method of an electronic device. A seed layer is formed on a substrate. After patterning the seed layer to form a plurality of sub-seed layers and a plurality of conductive lines, a metal layer is formed on a plurality of the sub-seed layers. The sub-seed layers include a first sub-seed layer and a second sub-seed layer, and the first sub-seed layer and the second sub-seed layer are separated from each other.

First claim

What is claimed is:

1. A method for manufacturing an electronic device, comprising:
providing a substrate;
forming a seed layer on the substrate;
patterning the seed layer to form a plurality of sub-seed layers and a plurality of conductive lines, wherein each of the conductive lines has at least one turn; and
forming a metal layer on at least one of the sub-seed layers after patterning the seed layer,
wherein, the sub-seed layers comprise a first sub-seed layer and a second sub-seed layer surrounds the first sub-seed layer, the first sub-seed layer comprises a plurality of main regions, the second sub-seed layer comprises a plurality of peripheral regions, one of the plurality of main regions is disposed between two of the plurality of peripheral regions, two of the plurality of conductive lines is disposed between the one of the main regions and one of the two of the plurality of peripheral regions, the one of the main regions and one of the two of the plurality of peripheral regions is connected by the two of the plurality of conductive lines, and the one of the main regions of the first sub-seed layer and the two of the plurality of peripheral regions of the second sub-seed layer are separated from each other,
wherein a length difference between the two of the plurality of conductive lines is not greater than 15%.

2. The method for manufacturing the electronic device of claim 1 , wherein the metal layer is formed on the conductive lines to become traces.

3. The method for manufacturing the electronic device of claim 1 , wherein the metal layer is formed on the first sub-seed layer.

4. The method for manufacturing the electronic device of claim 1 , wherein the first sub-seed layer comprises a plurality of protrusions.

5. The method for manufacturing the electronic device of claim 4 , wherein at least one of the protrusions has a chamfer.

6. The method for manufacturing the electronic device of claim 5 , wherein the chamfer has an angle between 30° and 150°.

7. The method for manufacturing the electronic device of claim 4 , wherein there is a gap disposed between any adjacent two of the protrusions.

8. The method for manufacturing the electronic device of claim 4 , wherein one of the protrusions is electrically connected to the second sub-seed layer through one of the conductive lines.

9. The method for manufacturing the electronic device of claim 1 , further comprising:
patterning the metal layer to obtain a patterned metal layer.

10. The method for manufacturing the electronic device of claim 9 , wherein an insulating layer is formed on the patterned metal layer.

11. The method for manufacturing the electronic device of claim 10 , further comprising:
patterning the insulating layer.

12. The method for manufacturing the electronic device of claim 11 , wherein the insulating layer and the patterned metal layer together form a functional stack.

13. The method for manufacturing the electronic device of claim 1 , wherein the seed layer which is patterned comprises a third sub-seed layer disposed between adjacent two of the main regions.

14. The method for manufacturing the electronic device of claim 13 , wherein the third sub-seed layer is connected to at least one of the conductive lines.

15. The method for manufacturing the electronic device of claim 14 , wherein the first sub-seed layer is electrically connected to the third sub-seed layer through the at least one of the conductive lines.

16. The method for manufacturing the electronic device of claim 14 , wherein the third sub-seed layer is electrically connected to the second sub-seed layer through the at least one of the conductive lines.

Assignees

• Innolux Corp

Inventors

• Ting Chin-Lung
• Wang Cheng-Chi
• Chang Yu-Jen
• Wang Ju-Li

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title