Memory device and operating method of the memory device for controlling a channel voltage

Patent metadata

Field	Value
Publication number	US-12374387-B2
Application number	US-202217986628-A
Country	US
Kind code	B2
Filing date	Nov 14, 2022
Priority date	May 31, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A memory device, and a method of operating the memory device, includes a memory block including strings formed between bit lines and a source line and includes a peripheral circuit configured to perform a read operation of a selected memory cell included in a selected string among the strings. The peripheral circuit includes page buffers configured to increase a voltage of channels of the strings by applying a first precharge voltage to the bit lines in a set-up phase of the read operation, apply a second precharge voltage lower than the first precharge voltage to the bit lines in a read phase of the read operation, and discharge the bit lines in a discharge phase of the read operation.

First claim

What is claimed is:

1. A memory device comprising:
a memory block including strings formed between bit lines and a source line; and
a peripheral circuit configured to perform a read operation of a selected memory cell included in a selected string among the strings,
wherein the peripheral circuit includes page buffers configured to:
increase a voltage of channels of the strings by applying a first precharge voltage to the bit lines in a set-up phase of the read operation;
apply a second precharge voltage lower than the first precharge voltage to the bit lines in a read phase of the read operation; and
discharge the bit lines in a discharge phase of the read operation,
wherein, in the set-up phase, the peripheral circuit is configured to apply a pass voltage to both selected word lines and unselected word lines connected to the strings, and
wherein, in the read phase, the peripheral circuit is configured to float a channel of an unselected string of the strings.

2. The memory device of claim 1 , wherein, in the set-up phase, the peripheral circuit is configured to apply a voltage of OV to the source line.

3. The memory device of claim 2 , wherein, in the set-up phase, the peripheral circuit is configured to turn on drain select transistors which are connected between the bit lines and memory cells in the strings.

4. The memory device of claim 2 , wherein, in the set-up phase, the peripheral circuit is configured to turn off source select transistors which are connected between the source line and memory cells in the strings.

5. The memory device of claim 1 , wherein, to float the channel of the unselected string, the peripheral circuit is configured to turn off an unselected drain select transistor and an unselected source select transistor, which are included in the unselected string.

6. The memory device of claim 1 , wherein, in the read phase, the peripheral circuit is configured to apply a read voltage to a selected word line connected to the selected memory cell included in the selected string.

7. The memory device of claim 1 , wherein, in the set-up phase, the peripheral circuit is configured to float the source line.

8. The memory device of claim 7 , wherein, in the set-up phase, the peripheral circuit is configured to turn on drain select transistors which are connected between the bit lines and memory cells in the strings and turn on source select transistors which are connected between the source line and memory cells in the strings.

9. The memory device of claim 8 , wherein, in the set-up phase, the peripheral circuit is configured to apply a read voltage to a selected word line among the word lines, when the pass voltage is applied to the word lines.

10. The memory device of claim 1 , wherein, before the discharge phase is performed, the peripheral circuit is configured to perform an equalizing phase for equally adjusting voltages of word lines connected to the strings.

11. The memory device of claim 1 , wherein, in the discharge phase, the peripheral circuit is configured to discharge a source select line, word lines, and a drain select line, which are connected to the strings.

12. A method of operating a memory device, the method comprising:
increasing a channel voltage by applying a first precharge voltage to bit lines electrically coupled to channels of strings;
applying a second precharge voltage lower than the first precharge voltage to the bit lines, when the channel voltage is increased;
applying a read voltage to a selected word line among word lines arranged between the bit lines and a source line; and
discharging the bit lines and the word lines,
wherein, in increasing the channel voltage, applying a pass voltage to both selected word lines and unselected word lines which connected to the strings, and
wherein, in applying the second precharge voltage to the bit lines, unselected drain select transistors and unselected source select transistors, which are connected to the unselected string, are turned off.

13. The method of claim 12 , wherein, in increasing the channel voltage, a drain select transistor is turned on by applying a turn-on voltage to a drain select line adjacent to the bit lines, and a source select transistor is turned off by applying a turn-off voltage to a source select line adjacent to the source line, when a voltage of 0V is applied to the source line.

14. The method of claim 12 , wherein, in increasing the channel voltage, a drain select transistor is turned on by applying a turn-on voltage to a drain select line adjacent to the bit lines, and a source select transistor is turned on by applying a turn-on voltage to a source select line adjacent to the source line, when the source line is floated.

15. The method of claim 12 , wherein, when the read voltage is applied to the selected word line, a pass voltage is applied to unselected word lines.

16. The method of claim 12 , wherein an equalizing phase for equally adjusting voltages of the word lines is further included between the applying of the read voltage and the discharging.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• H10B41/23

  with source and drain on different levels, e.g. with sloping channels · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title