Using a next fetch predictor circuit with short branches and return fetch groups

Patent metadata

Field	Value
Publication number	US-12373215-B2
Application number	US-202217814729-A
Country	US
Kind code	B2
Filing date	Jul 25, 2022
Priority date	Jul 25, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

An apparatus includes an instruction cache circuit and an instruction fetch circuit. The instruction fetch circuit is configured to retrieve, from the instruction cache circuit, a fetch group that includes a plurality of instructions for execution by a processing circuit, and to make a determination that the fetch group includes a control transfer instruction that is predicted to be taken. A target address associated with the control transfer instruction is directed to an instruction within the fetch group. The instruction fetch circuit is further configured to, based on the determination, alter instructions within the fetch group in a manner that is based on a type of the control transfer instruction.

First claim

What is claimed is:

1. An apparatus, comprising:
an instruction cache circuit;
a next fetch predictor circuit that includes an entry corresponding to a fetch address, wherein the entry includes a first target address of a first control transfer instruction in a fetch group associated with the fetch address; and
an instruction fetch circuit configured to:
retrieve, from the instruction cache circuit based on the fetch address, the fetch group that includes a plurality of instructions for execution by a processing circuit;
determine, based on the entry, that the fetch group includes the first control transfer instruction that is predicted to be taken and an instruction at the first target address; and
based on the determination:
add a tag to the entry, wherein the tag is indicative that the first target address and the first control transfer instruction are included in the fetch group;
determine that a second control transfer instruction is included in the fetch group, the second control transfer instruction having a second target address; and
update the entry to include the second target address in place of the first target address.

2. The apparatus of claim 1 , wherein the instruction fetch circuit is further configured to:
in response to a determination that the first control transfer instruction is a call instruction:
identify an address of an instruction after the call instruction as the first target address;
store, in an instruction buffer circuit, a first portion of the fetch group that includes instructions from a beginning of the fetch group to the call instruction;
store, in a return fetch stack circuit that is different from the instruction buffer circuit, a second portion of the fetch group starting with the instruction at the first target address; and
retrieve a next fetch group based on a target address of the call instruction.

3. The apparatus of claim 1 , wherein the instruction fetch circuit is further configured to:
in response to a determination that the first control transfer instruction is a backward branch instruction, store a first portion of the fetch group followed by a second portion of the fetch group in an instruction buffer; and
wherein the first and second portions of the fetch group each include at least the instruction at the first target address and the backward branch instruction.

4. The apparatus of claim 3 , wherein to determine that the first control transfer instruction is the backward branch instruction, the instruction fetch circuit is configured to determine that the backward branch instruction is taken more than a threshold number of consecutive times.

5. The apparatus of claim 1 , wherein the instruction fetch circuit is further configured to:
in response to a determination that the first control transfer instruction is a forward branch instruction:
store a first portion of the fetch group in an instruction buffer circuit, wherein the first portion of the fetch group includes instructions from a beginning of the fetch group to the forward branch instruction;
identify a second portion of the fetch group starting with the instruction at the first target address; and
store the second portion of the fetch group consecutive to the first portion in the instruction buffer circuit, omitting instructions between the forward branch instruction and the instruction at the first target address.

6. The apparatus of claim 1 , wherein the instruction fetch circuit is further configured to:
after a subsequent retrieval of the fetch group, determine, using the tag, that the fetch group includes the first control transfer instruction and the instruction at the first target address.

7. The apparatus of claim 6 , wherein the instruction fetch circuit is further configured to:
after an initial retrieval of the fetch group, retrieve a next fetch group based on the first target address; and
after the subsequent retrieval of the fetch group, skip a retrieval of the next fetch group based on the first target address.

8. A method, comprising:
storing, by a next fetch predictor circuit, a first target address of a first control transfer instruction into an entry corresponding to a fetch address;
retrieving, by an instruction fetch circuit using the fetch address, a fetch group that includes a plurality of instructions for execution by a processing circuit;
determining, by the instruction fetch circuit, that the fetch group includes the first control transfer instruction that is predicted to be taken and that the first target address is directed to an instruction included within the fetch group;
based on the determining that the fetch group includes the first control transfer instruction and the first target address:
adding a tag to the entry corresponding to the fetch address in the next fetch predictor circuit;
identifying a second target address of a second control transfer instruction in the fetch group; and
replacing the first target address with the second target address in the entry.

9. The method of claim 8 , wherein, in response to determining that the first control transfer instruction is a call instruction: using an address of an instruction that is subsequent to the call instruction as the first target address;
storing, in an instruction buffer circuit, a first portion of the fetch group that includes instructions from a beginning of the fetch group to the call instruction; and
storing, in a return fetch stack circuit that is different from the instruction buffer circuit, a second portion of the fetch group starting with the instruction at the first target address.

10. The method of claim 9 , further comprising:
retrieving a next fetch group based on a target address of the call instruction; and
in response to determining the next fetch group includes a return instruction, retrieving the second portion from the return fetch stack circuit.

11. The method of claim 8 , wherein, in response to determining that the first control transfer instruction is a backward branch instruction:
storing a first portion of the fetch group followed by a second portion of the fetch group in an instruction buffer, wherein the first and second portions of the fetch group each include at least the instruction at the first target address and the backward branch instruction.

12. The method of claim 11 , further comprising determining that the first control transfer instruction is the backward branch instruction in response to determining that the backward branch instruction is taken more than a threshold number of consecutive times.

13. The method of claim 8 , wherein, in response to determining that the first control transfer instruction is a forward branch instruction: storing the fetch group in an instruction buffer circuit by omitting instructions between the forward branch instruction and the instruction at the first target address.

14. A system comprising:
an instruction cache circuit configured to store a plurality of instructions;
a next fetch predictor circuit configured to store, in an entry corresponding to a particular fetch address, a first target address of a first control transfer instruction in a fetch group; and
an instruction fetch circuit configured to:
retrieve, using the particular fetch address, the fetch group from the plurality of instructions in the instruction cache circuit;
determine, using the entry from the next fetch predictor circuit, that the first control transfer instruction is predicted to be taken and that the first target address is included in the fetch group;
in response to the determination:
tag the entry in the next fetch predictor circ

Assignees

• Apple Inc

Inventors

• Choudhary Niket K
• Brown Mary D
• Schuchman Ethan R
• Hall Ronald P
• Kountanis Ian D
• Holman Douglas C
• Kim Ilhyun
• Kumar Abhishek
• Zangeneh Kamali Siavash

Classifications

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/0886

  Variable-length word access · CPC title