Efficient central processing unit (cpu) return address and instruction cache

Patent metadata

Field	Value
Publication number	US-2015205613-A1
Application number	US-201414160280-A
Country	US
Kind code	A1
Filing date	Jan 21, 2014
Priority date	Jan 21, 2014
Publication date	Jul 23, 2015
Grant date	—

Abstract

A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is configured to fetch instructions from memory into the instruction pre-fetch buffer. The instruction decode unit is coupled to the instruction pre-fetch buffer and upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction. Upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from beginning at an address after the N instruction words.

First claim

What is claimed is:

1 . A processor, comprising:
an instruction fetch unit including an instruction pre-fetch buffer, the instruction fetch unit configured to fetch instructions from memory into the instruction pre-fetch buffer; and an instruction decode unit coupled to the instruction pre-fetch buffer, the instruction decode unit, upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction; wherein, upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from the memory beginning at an address after the N instruction words.

2 . The processor of claim 1 , wherein the software module is a sub-routine.

3 . The processor of claim 1 , wherein the software module is an interrupt service routine.

4 . The process of claim 1 , wherein the preserved N instruction words correspond to at least one instruction.

5 . The processor of claim 1 , wherein the instruction fetch unit further comprises a return instruction cache, and wherein the next N instruction words of the instruction pre-fetch buffer are preserved in the return instruction cache.

6 . The processor of claim 1 , wherein the instruction fetch unit is further configured to preserve a location of the instruction pre-fetch buffer where the N instruction words are stored during execution of the software module.

7 . The processor of claim 1 , wherein the instruction pre-fetch buffer comprises a reserved portion for preserving the next N instruction words.

8 . The processor of claim 1 further comprising a return address register, wherein the instruction decode unit, upon decoding the call instruction from the instruction pre-fetch buffer, causes an address of the memory after the call instruction to be saved in the return address register, and wherein upon completion of execution of the software module, the instruction fetch unit retrieves the saved address from the return address register, and computes the address after the N instruction words for fetching based on the saved address.

9 . A method, comprising:
fetching a plurality of instructions from memory into an instruction pre-fetch buffer; upon decoding a first call instruction from the instruction pre-fetch buffer, the first call instruction causing a first software module to be executed, preserving next N1 instruction words of the instruction pre-fetch buffer through at least completed execution of the first software module, where N1 is greater than or equal to one; fetching, decoding, and executing instructions of the first software module beginning at an address indicated by the first call instruction; and upon completion of the first software module, concurrently decoding and executing the preserved N1 instruction words while fetching instruction words from the memory beginning at an address immediately after the N1 instruction words.

10 . The method of claim 9 , wherein the first software module is a sub-routine.

11 . The method of claim 9 , wherein the first software module is an interrupt service routine.

12 . The method of claim 9 , wherein preserving the next N1 instruction words of the instruction pre-fetch buffer comprises copying the next N1 instruction words from the instruction pre-fetch buffer to a return instruction cache.

13 . The method of claim 9 , wherein preserving the next N1 instruction words of the instruction pre-fetch buffer comprises reserving an area of the next N1 instruction words in the instruction pre-fetch buffer.

14 . The method of claim 9 further comprising:
upon decoding the first call instruction, saving an address of the memory after the first call instruction into a return address register;
upon completion of the first software module, retrieving the saved address from the return address register; and
computing the address immediately after the next N1 instruction words based on the retrieved address.

15 . The method of claim 9 , wherein the first software module comprises a second call instruction, and wherein the method further comprises:
upon decoding the second call instruction from the instruction pre-fetch buffer, the second call instruction causing a second software module to be executed, preserving next N2 instruction words of the instruction pre-fetch buffer in conjunction with the preserved next N1 instruction words through at least completed execution of the second software module, where N1 and N2 are independent; fetching, decoding, and executing instructions of the second software module beginning at an address indicated by the second call instruction; and upon completion of the second software module, concurrently decoding and executing the preserved N2 instruction words while fetching instruction words from the memory beginning at an address immediately after the N2 instruction words.

16 . The method of claim 9 , wherein the software module comprises a second call instruction, and wherein the method further comprises:
upon decoding the second call instruction from the instruction pre-fetch buffer, the second call instruction causing a second software module to be executed, replacing the preserved next N1 instruction words with the next N2 instruction words of the instruction pre-fetch buffer, where N1 and N2 are independent; fetching, decoding, and executing instructions of the second software module beginning at an address indicated by the second call instruction; and upon completion of the second software module, concurrently decoding and executing the preserved N2 instruction words while fetching instruction words from the memory beginning at an address immediately after the N2 instruction words.

17 . The method of claim 9 , wherein the first software module is a sub-routine of a multi-level nested sub-routine.

18 . A processor, comprising:
an instruction fetch unit, comprising:
a return instruction cache;
an instruction pre-fetch buffer; and
a pre-decoder coupled to the instruction pre-fetch buffer and the return instruction cache;
wherein, the instruction fetch unit is configured to fetch instructions from memory into the instruction pre-fetch buffer, and
wherein the pre-decoder, upon decoding a call instruction from the instruction pre-fetch buffer, initiates copying of next N instruction words from the instruction pre-fetch buffer into the return instruction cache, where N is an integer value greater than or equal to one, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction;
an instruction decode unit coupled to the instruction pre-fetch buffer and the return instruction cache, wherein the instruction decode unit is configured to decode the fetched instructions; and an instruction execution unit coupled to the instruction decode unit and configured to execute the decoded instructions; wherein, upon completion of execution of the software module, the instruction decode unit begins to decode the saved N instruction words in the return instruction cache while the instruction fetch unit concurrently fetches instructions from the memory beginning at an

Assignees

• Texas Instruments Deutschland

Inventors

• Bhatia Shrey
• Wiencke Christian

Classifications

• G06F9/3808 Primary

  for instruction reuse, e.g. trace cache, branch target cache · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30054

  Unconditional branch instructions · CPC title

• G06F9/3814

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/3804 Primary

  for branches, e.g. hedging, branch folding · CPC title