Skew detection and compensation for high speed I/O links

Patent metadata

Field	Value
Publication number	US-12372574-B2
Application number	US-202117353453-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Jun 21, 2021
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

An apparatus may comprise a skew detection circuit to sample a common mode voltage of a differential signal, wherein the sampled common mode voltage is indicative of an amount of skew between a first signal of the differential signal and a second signal of the differential signal; and a skew compensation circuit to adjust a delay of the first signal or the second signal based on the sampled common mode voltage to reduce the amount of skew.

First claim

What is claimed is:

1. An apparatus comprising:
a skew detection circuit to sample a common mode voltage of a differential signal, wherein the sampled common mode voltage is indicative of an amount of skew between a first signal of the differential signal and a second signal of the differential signal;
a skew compensation circuit to adjust a delay of the first signal or the second signal based on the sampled common mode voltage to reduce the amount of skew; and
a selection circuit to selectively couple an output of the skew compensation circuit to the skew detection circuit or to a receiver path to detect data transmitted by the differential signal.

2. The apparatus of claim 1 , wherein the skew compensation circuit comprises a first adjustable capacitor to couple to the first signal and a second adjustable capacitor to couple to the second signal.

3. The apparatus of claim 2 , wherein the skew compensation circuit is to adjust the first or second adjustable capacitor to reduce the amount of skew based on the sampled common mode voltage.

4. The apparatus of claim 2 , wherein the skew compensation circuit further comprises an analog buffer.

5. The apparatus of claim 4 , wherein the analog buffer comprises a passive continuous time linear equalizer.

6. The apparatus of claim 1 , wherein the skew detection circuit comprises a common mode voltage measurement circuit comprising a feedback resistor, a first resistor coupled to the first signal, and a second resistor coupled to the second signal.

7. The apparatus of claim 6 , wherein the first and second resistor each have the same resistance value.

8. The apparatus of claim 1 , wherein the skew detection circuit is to determine a maximum common mode voltage and a minimum common mode voltage of the sampled common mode voltage and to instruct the skew compensation circuit to adjust the delay of the first signal or the second signal based on the maximum common mode voltage and the minimum common mode voltage.

9. The apparatus of claim 1 , wherein the skew detection circuit is to sample the common mode voltage at a plurality of sampling time points throughout a period of a receiver clock.

10. A system comprising:
a receiver comprising:
a skew detection circuit to sample a common mode voltage of a differential signal, wherein the sampled common mode voltage is indicative of an amount of skew between a first signal of the differential signal and a second signal of the differential signal;
a skew compensation circuit to adjust a delay of the first signal or the second signal based on the sampled common mode voltage to reduce the amount of skew;
a receiver path to detect data transmitted by the differential signal; and
a selection circuit to selectively couple an output of the skew compensation circuit to the skew detection circuit or to the receiver path; and

a transmitter to transmit the differential signal over a pair of communication paths to the receiver.

11. The system of claim 10 , wherein the skew compensation circuit comprises a first adjustable capacitor to couple to the first signal and a second adjustable capacitor to couple to the second signal.

12. The system of claim 11 , wherein the skew compensation circuit is to adjust the first or second adjustable capacitor to reduce the amount of skew based on the sampled common mode voltage.

13. The system of claim 10 , further comprising at least one of a battery, display, or network interface controller communicatively coupled to a processor comprising the receiver.

14. A method comprising:
sampling a common mode voltage of a differential signal, wherein the sampled common mode voltage is indicative of an amount of skew between a first signal of the differential signal and a second signal of the differential signal;
adjusting a delay of the first signal or the second signal based on the sampled common mode voltage to reduce the amount of skew; and
selectively coupling the differential signal to a skew detection circuit or a receiver path.

15. The method of claim 14 , further comprising deciding whether to adjust a first capacitor or a second capacitor based on the sampled common mode voltage to reduce the amount of skew.

16. The method of claim 14 , further comprising determining a maximum and minimum common mode voltage from the sampled common mode voltage and adjusting the delay of the first signal or the second signal based on the maximum and minimum common mode voltages.

17. The method of claim 14 , wherein sampling the common mode voltage of the differential signal comprises sampling the common mode voltage at a plurality of sampling time points throughout a period of a receiver clock.

Assignees

• Intel Corp

Inventors

• Guo Jong-Ru
• Li Jingbo
• Ye Xiaoning
• Wu Zuoguo
• Heck Howard L

Classifications

• G01R31/31706

  involving differential digital signals, e.g. testing differential signal circuits, using differential signals for testing · CPC title

• H04L25/0276 Primary

  Arrangements for coupling common mode signals · CPC title

• H04L25/03006

  Arrangements for removing intersymbol interference · CPC title

• G01R31/31725 Primary

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G05F1/625 Primary

  wherein it is irrelevant whether the variable actually regulated is AC or DC · CPC title