Pixel circuit having increased capacitance and display device including the same

Patent metadata

Field	Value
Publication number	US-12369456-B2
Application number	US-202418634558-A
Country	US
Kind code	B2
Filing date	Apr 12, 2024
Priority date	Dec 1, 2020
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A display device includes a first lower electrode disposed on a base substrate, a first upper electrode disposed on the first lower electrode, overlapping the first lower electrode in a plan view, including a silicon semiconductor, and constituting a first capacitor together with the first lower electrode, a second lower electrode disposed on the first upper electrode, and a second upper electrode disposed on the second lower electrode, overlapping the second lower electrode in a plan view, including an oxide semiconductor, and constituting a second capacitor together with the second lower electrode.

First claim

What is claimed is:

1. A pixel circuit comprising:
a first transistor including a first terminal, a second terminal, and a gate terminal, wherein the gate terminal is connected to a first node;
a second transistor including a first terminal receiving a data voltage, a second terminal connected to the first terminal of the first transistor, and a gate terminal receiving a first gate signal;
a third transistor including a first terminal connected to the second terminal of the first transistor, a second terminal connected to the first node, a gate terminal receiving a second gate signal, and a back-gate terminal receiving the second gate signal;
a first capacitor including a first terminal receiving a high power voltage and a second terminal connected to the first node; and
a second capacitor connected in parallel with the first capacitor between the high power voltage and the first node.

2. The pixel circuit of claim 1 , wherein the first transistor further comprises a back-gate terminal connected to the first node.

3. The pixel circuit of claim 2 , wherein the first transistor and the second transistor are PMOS transistors and the third transistor is an NMOS transistor.

4. A display device comprising:
a light emitting diode connected between a first power voltage line and a second power voltage line which supplies a voltage lower than that of the first power voltage line;
a first transistor serially connected to the light emitting diode between the first power voltage line and the second power voltage line, the first transistor including a first gate electrode, a first active layer which includes a first source electrode and a first drain electrode, and a first back-gate terminal connected to the first gate electrode;
a second transistor connected between the first gate electrode and the first drain electrode of the first transistor, the second transistor including a second gate electrode which receives a gate signal and a second active layer which includes a second source electrode connected to the first drain electrode and a second drain electrode connected to the first gate electrode;
a first capacitor, the first capacitor including a first terminal connected to the first power voltage line and a second terminal connected to the first gate electrode; and
a second capacitor, the second capacitor including a third terminal connected to the first power voltage line and a fourth terminal connected to the first gate electrode,
wherein the first back-gate terminal is disposed on a same layer as the first terminal.

5. The display device of claim 4 , wherein the first active layer and the second terminal are disposed on a same layer and are formed of a same material.

6. The display device of claim 4 , wherein the second transistor further including a second back-gate terminal connected to the second gate electrode and disposed on a same layer as the first gate electrode.

7. The display device of claim 6 , wherein the first terminal and the second terminal do not overlap the second gate electrode in a plan view.

8. The display device of claim 4 , wherein the third terminal and the second active layer are disposed on a same layer and are formed of a same material.

9. The display device of claim 4 , wherein the first terminal and the second terminal overlap the second gate electrode in a plan view.

10. An electronic device, comprising:
a display device; and
a power module that supplies power to the display device,
wherein the display device includes:
a light emitting diode connected between a first power voltage line and a second power voltage line which supplies a voltage lower than that of the first power voltage line;
a first transistor serially connected to the light emitting diode between the first power voltage line and the second power voltage line, the first transistor including a first gate electrode, a first active layer which includes a first source electrode and a first drain electrode, and a first back-gate terminal connected to the first gate electrode;
a second transistor connected between the first gate electrode and the first drain electrode of the first transistor, the second transistor including a second gate electrode which receives a gate signal and a second active layer which includes a second source electrode connected to the first drain electrode and a second drain electrode connected to the first gate electrode;
a first capacitor, the first capacitor including a first terminal connected to the first power voltage line and a second terminal connected to the first gate electrode; and
a second capacitor, the second capacitor including a third terminal connected to the first power voltage line and a fourth terminal connected to the first gate electrode, and
wherein the first back-gate terminal is disposed on a same layer as the first terminal.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Myeongho
• Kim Yeonhong
• Kim Jaybum
• Son Kyoung Seok
• Lee Sunhee
• Lee Seungjun
• Lee Seunghun
• Lim Jun Hyung

Classifications

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title