Semiconductor device

Patent metadata

Field	Value
Publication number	US-12369381-B2
Application number	US-202017639528-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Sep 30, 2019
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A semiconductor device includes a chip, an electrode that is formed on the chip, an inorganic insulating layer that covers the electrode and has a first opening exposing the electrode, an organic insulating layer that covers the inorganic insulating layer, has a second opening surrounding the first opening at an interval from the first opening, and exposes an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and an Ni plating layer that covers the electrode inside the first opening and covers the inner peripheral edge of the inorganic insulating layer inside the second opening.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a chip;
an electrode that is formed on the chip;
an inorganic insulating layer that covers the electrode and exposes the electrode from a first opening;
an organic insulating layer that covers the inorganic insulating layer, has a second opening having an opening end that is formed at an interval from an opening end of the first opening, and exposes an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening; and
an Ni plating layer that covers the electrode inside the first opening and covers the inner peripheral edge of the inorganic insulating layer inside the second opening, wherein
the inorganic insulating layer has a first outer wall, and
the organic insulating layer has a second outer wall positioned more inward than the first outer wall of the inorganic insulating layer.

2. The semiconductor device according to claim 1 , wherein the Ni plating layer is formed at an interval toward an inorganic insulating layer side from the opening end of the second opening.

3. The semiconductor device according to claim 1 , further comprising:
an outer surface plating layer that covers an outer surface of the Ni plating layer inside the second opening.

4. The semiconductor device according to claim 3 , wherein the outer surface plating layer covers the Ni plating layer at an interval toward the inorganic insulating layer side from the opening end of the second opening.

5. The semiconductor device according to claim 3 , wherein the outer surface plating layer has a thickness less than a thickness of the Ni plating layer.

6. The semiconductor device according to claim 1 , wherein the Ni plating layer covers the inner peripheral edge of the inorganic insulating layer at an interval from the organic insulating layer inside the second opening.

7. The semiconductor device according to claim 1 , wherein the inner peripheral edge of the inorganic insulating layer has a width that exceeds a thickness of the inorganic insulating layer.

8. The semiconductor device according to claim 3 , wherein the outer surface plating layer has a portion that covers the inner peripheral edge of the inorganic insulating layer.

9. The semiconductor device according to claim 3 , wherein the outer surface plating layer covers the Ni plating layer at an interval from the organic insulating layer.

10. The semiconductor device according to claim 1 , wherein the chip is constituted of an SiC chip.

11. The semiconductor device according to claim 1 , wherein the second outer wall of the organic insulating layer is formed in a curved shape depressed toward the inorganic insulating layer.

12. The semiconductor device according to claim 1 , further comprising:
a transistor that is formed in the chip.

13. The semiconductor device according to claim 12 , wherein the transistor includes unit cells that extend in a stripe shape.

14. The semiconductor device according to claim 13 , wherein the transistor includes trench gate structures that extend in a stripe shape along the unit cells.

15. The semiconductor device according to claim 14 , wherein
the chip has a rectangular shape as viewed in a plan view, and
the trench gate structures extends along a short side of the chip.

16. The semiconductor device according to claim 1 , wherein the chip has a rectangular shape as viewed in a plan view.

17. The semiconductor device according to claim 1 , wherein
the chip that has a first main surface on one side and a second main surface on the other side,
the electrode covers the first main surface,
a back surface electrode covers the second main surface, and
the back surface electrode includes a Ti layer.

18. The semiconductor device according to claim 1 , wherein
the chip has a first main surface on one side and a second main surface on the other side,
the electrode covers the first main surface,
a back surface electrode covers the second main surface, and
the back surface electrode includes an Ni layer.

19. A semiconductor package comprising:
a package main body that is made of resin;
a plate shaped member that includes copper and that is arranged in the package main body; and
the semiconductor device according to claim 1 that is arranged in the package main body.

20. The semiconductor package according to claim 19 , wherein
the electrode includes a source pad electrode, and
the plate shaped member is electrically connected to the source pad electrode.

Assignees

• Rohm Co Ltd

Inventors

• Yamanaka Takaaki
• Nakano Yuki
• Yamamoto Kenji

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10D64/0123

  to silicon carbide · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title