Semiconductor device and manufacturing method of same

Patent metadata

Field	Value
Publication number	US-2016240484-A1
Application number	US-201615139825-A
Country	US
Kind code	A1
Filing date	Apr 27, 2016
Priority date	Jul 17, 2012
Publication date	Aug 18, 2016
Grant date	—

Abstract

To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor substrate; a first wire over the semiconductor substrate; an insulating film formed over the semiconductor substrate and the first wire, and having an opening so as to expose an upper surface part of the first wire; a second wire over the opening connected with the first wire and formed over the insulating film; and a bonding wire connected with the second wire, wherein the second wire is a stack of a layer of Cu film, Ni film and Pd film in order from the first wire, and wherein the bonding wire is connected with the Pd film and a connection part is outside from the opening in plan view and overlaps the insulating film.

2 . The semiconductor device according to claim 1 ,
wherein the semiconductor substrate includes a substrate, a plurality of semiconductor elements, a plurality of interlayer insulating films, and a plurality of wirings.

3 . The semiconductor device according to claim 1 ,
wherein the Ni film has a film thickness smaller than that of the Cu film.

4 . The semiconductor device according to claim 1 ,
wherein the connection part is located outside from the first wiring.

5 . The semiconductor device according to claim 1 ,
wherein the insulating film including polyimide layer and the connection part is located over the polyimide layer.

6 . The semiconductor device according to claim 1 ,
wherein the Cu film, the Ni film and the Pd film have the same pattern shape in a plan view.

7 . The semiconductor device according to claim 1 , wherein the bonding wire contains Cu.

8 . The semiconductor device according to claim 1 , wherein the Ni film has a film thickness smaller than that of the Cu film.

9 . The semiconductor device according to claim 1 , wherein the semiconductor device is sealed with a resin.

10 . A manufacturing method a semiconductor device, comprising:
(a) providing a semiconductor substrate having an electrode pad exposed from an upper surface of the semiconductor substrate; (b) forming an insulating film over the semiconductor substrate and the first wire, and having an opening so as to expose an upper surface part of the first wire; (c) forming a seed film over the insulating film and in contact with an upper surface of the electrode pad; (d) forming a resist pattern having a second opening exposing the upper surface electrode pad and an upper surface of the insulating film over the seed film; (e) forming a Cu film, an Ni film, and a Pd film successively over the seed film exposed from the resist pattern by using plating; (f) after the step (e), removing the resist pattern; and (g) coupling directly a bonding wire to an upper surface of the Pd film, wherein the bonding wire is connected with the Pd film and a connection part is outside from the opening in plan view and overlaps the insulating film.

11 . The manufacturing method according to claim 10 ,
wherein the Pd film has a film thickness smaller than that of the Ni film.

12 . The manufacturing method according to claim 10 ,
wherein the Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.

13 . The manufacturing method according to claim 10 ,
wherein the bonding wire contains Cu.

14 . The manufacturing method according to claim 10 ,
wherein the Ni film has a film thickness smaller than that of the Cu film.

Assignees

• Renesas Electronics Corp

Inventors

• Shigihara Hisao
• Shigihara Hiromi
• Yajima Akira
• Tsukamoto Hiroshi

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title