Info packages including thermal dissipation blocks

Patent metadata

Field	Value
Publication number	US-12368148-B2
Application number	US-202418602533-A
Country	US
Kind code	B2
Filing date	Mar 12, 2024
Priority date	Aug 6, 2021
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first interconnect structure, the first interconnect structure comprising:
a first electrical portion comprising first conductive elements embedded in first dielectric layers; and
a first dummy portion comprising second conductive elements embedded in the first dielectric layers;

attaching a first integrated circuit die to a first side of the first interconnect structure, the first integrated circuit die being displaced from the first dummy portion of the first interconnect structure;
forming a second interconnect structure over the first integrated circuit die, the second interconnect structure being electrically connected to the first electrical portion of the first interconnect structure; and
attaching a semiconductor package to a second side of the first interconnect structure, electrical connectors electrically connecting the first electrical portion to the semiconductor package, thermal dissipation connectors electrically connecting the first dummy portion to the semiconductor package.

2. The method of claim 1 , wherein the first dummy portion of the first interconnect structure is electrically isolated from the first electrical portion of the first interconnect structure.

3. The method of claim 1 , wherein the semiconductor package comprises an interposer substrate and a die layer, and wherein the die layer comprises a second integrated circuit die embedded in a molding compound.

4. The method of claim 3 , wherein the interposer substrate comprises:
a second electrical portion comprising third conductive elements embedded in a dielectric substrate; and
a second dummy portion comprising fourth conductive elements embedded in the dielectric substrate.

5. The method of claim 4 , wherein the fourth conductive elements comprise through package vias extending through the dielectric substrate and the molding compound, wherein a thermal dissipation block comprises the second conductive elements of the first interconnect structure, the thermal dissipation connectors, the fourth conductive elements, and the through package vias, and wherein the thermal dissipation block is electrically isolated from the first conductive elements of the first interconnect structure, the first integrated circuit die, the electrical connectors, and the third conductive elements.

6. The method of claim 1 , wherein the thermal dissipation connectors comprise a first connector and a second connector, and wherein the first connector is in physical contact with the second connector.

7. The method of claim 1 , wherein in a plan view the thermal dissipation connectors extend beyond a footprint of the first integrated circuit die.

8. The method of claim 1 , further comprising forming external electrical connectors, wherein the external electrical connectors are electrically isolated from the second conductive elements and the thermal dissipation connectors.

9. A method of forming a semiconductor device, comprising:
forming a first interconnect structure and a thermal dissipation block over a substrate, the first interconnect structure comprising first conductive elements embedded in a first plurality of dielectric layers, the thermal dissipation block comprising second conductive elements embedded in the first plurality of dielectric layers;
forming metal posts over the first interconnect structure;
attaching a first die over the thermal dissipation block;
forming a second interconnect structure over the metal posts and the first die, the metal posts and the second interconnect structure electrically coupling the first interconnect structure to the first die, the thermal dissipation block being electrically isolated from the first interconnect structure and the metal posts;
removing the substrate;
forming conductive connectors over exposed portions of the first interconnect structure and the thermal dissipation block, the conductive connectors comprising electrical connectors and thermal dissipation connectors; and
attaching a semiconductor package to the conductive connectors, the semiconductor package comprising third conductive elements and fourth conductive elements, the third conductive elements being electrically connected to the first interconnect structure, the fourth conductive elements being electrically connected to the thermal dissipation block, the fourth conductive elements being electrically isolated from the third conductive elements.

10. The method of claim 9 , wherein in a plan view the first interconnect structure encircles the thermal dissipation block.

11. The method of claim 10 , wherein in the plan view the metal posts encircle the first die.

12. The method of claim 9 , wherein the semiconductor package comprises an interposer substrate and a die layer, the die layer comprising a second die embedded in a molding compound.

13. The method of claim 12 , wherein the second die is wire bonded to the third conductive elements.

14. The method of claim 12 , wherein the fourth conductive elements extend from a top surface of the interposer substrate to a bottom surface of the interposer substrate, wherein the top surface is in physical contact with the thermal dissipation connectors, and wherein the bottom surface is in physical contact with the molding compound.

15. The method of claim 12 , wherein at least one element of the fourth conductive elements extends through an entirety of the interposer substrate and the molding compound.

16. A method of forming a semiconductor device, comprising:
forming a first metallization layer over a substrate, the first metallization layer comprising first metal lines in a first interconnect region and first dummy metal lines in a thermal dissipation region;
forming a second metallization layer over the first metallization layer, the second metallization layer comprising second metal lines in the first interconnect region and second dummy metal lines in the thermal dissipation region;
forming a third metallization layer over the second metallization layer, the third metallization layer comprising third metal lines in the first interconnect region and third dummy metal lines in the thermal dissipation region;
forming a metal post over and electrically connected to the third metal lines;
attaching a first die over the thermal dissipation region, a dielectric layer being interposed between the first die and the third dummy metal lines along an entirety of a lower surface of the first die;
forming a second interconnect region over and electrically connecting the metal post to the first die; and
attaching a semiconductor package to the first metal lines, attaching the semiconductor package comprising:
removing the substrate;
electrically connecting redistribution lines of the semiconductor package to the first metal lines using electrical connectors; and
electrically connecting thermal dissipation features of the semiconductor package to the first dummy metal lines using thermal dissipation connectors.

17. The method of claim 16 , wherein attaching the semiconductor package further comprises depositing an underfill around the electrical connectors and the thermal dissipation connectors.

18. The method of claim 16 , wherein some of the thermal dissipation connectors are in physical contact with one another.

19. The method of claim 16 , wherein the first dummy metal lines, the second dummy metal lines, and the third dummy metal lines are electrically connected to one another.

20. T

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yu-Hao
• Chang Fong-Yuan
• Huang Po-Hsiang
• Lin Ching-Yi
• Lee Jyh Chwen Frank

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title