Diffusion barrier layer for conductive via to decrease contact resistance

Patent metadata

Field	Value
Publication number	US-12368103-B2
Application number	US-202318342889-A
Country	US
Kind code	B2
Filing date	Jun 28, 2023
Priority date	Mar 10, 2020
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

Some embodiments relate to a semiconductor structure including a dielectric layer over a substrate. A conductive body is disposed within the dielectric layer. The conductive body has a bottom surface continuously extending between opposing sidewalls. A first liner layer is disposed between the conductive body and the dielectric layer. The first liner layer extends along the opposing sidewalls of the conductive body. The first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a dielectric layer over a substrate;
a conductive body disposed within the dielectric layer, wherein the conductive body comprises a bottom surface continuously extending between opposing sidewalls;
a first liner layer disposed between the conductive body and the dielectric layer, wherein the first liner layer extends along the opposing sidewalls of the conductive body, and wherein the first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance; and
a second liner layer disposed between the first liner layer and the conductive body, wherein a top surface of the second liner layer is aligned with a top surface of the first liner layer and a top surface of the conductive body, and wherein a bottom surface of the first liner layer is aligned with a planar bottom surface of the second liner layer.

2. The semiconductor structure of claim 1 , wherein the bottom surface of the first liner layer is ring-shaped.

3. The semiconductor structure of claim 1 , wherein an area of the bottom surface of the conductive body is greater than an area of the bottom surface of the first liner layer.

4. The semiconductor structure of claim 1 , wherein the first liner layer and the second liner layer comprise a same material.

5. The semiconductor structure of claim 1 , wherein a thickness of the second liner layer is less than a thickness of the first liner layer.

6. The semiconductor structure of claim 1 , further comprising:
a first conductive structure underlying the conductive body; and
a conductive layer disposed between the first conductive structure and the conductive body, wherein a portion of the first liner layer directly contacts the conductive layer, wherein a region of the conductive layer is spaced between inner opposing sidewalls of the first liner layer, wherein an area of the region of the conductive layer is greater than an area of the portion of the first liner layer.

7. The semiconductor structure of claim 1 , wherein when viewed in cross-section the first liner layer comprises a first segment and a second segment disposed on opposing sides of the bottom surface of the conductive body, wherein the first liner layer is devoid of a lateral surface extending between the first and second segments.

8. The semiconductor structure of claim 1 , wherein the bottom surface of the first liner layer and the planar bottom surface of the second liner layer are respectively substantially parallel to a top surface of the substrate.

9. An integrated chip, comprising:
a first dielectric layer overlying a substrate;
a first conductive structure disposed in the first dielectric layer, wherein the first conductive structure comprises a capping layer on a lower conductive body, wherein the capping layer comprises a base segment and a pair of vertical segments over the base segment and disposed on opposing sides of the base segment;
a second dielectric layer over the first conductive structure; and
a second conductive structure disposed in the second dielectric layer, wherein the second conductive structure comprises a conductive body over the first conductive structure and a first liner layer between the conductive body and the second dielectric layer, wherein a lower surface of the conductive body directly overlies an upper surface of the base segment of the capping layer in a contact region, wherein a lower surface of the first liner layer abutting the first conductive structure is disposed outside the contact region, and wherein a segment of the first liner layer is adjacent to an individual vertical segment in the pair of vertical segments.

10. The integrated chip of claim 9 , wherein the first conductive structure is electrically coupled to the second conductive structure.

11. The integrated chip of claim 9 , wherein the first liner layer is devoid of a lateral surface continuously extending across the contact region.

12. The integrated chip of claim 9 , wherein a bottom surface of the conductive body is aligned with or extends below the lower surface of the first liner layer.

13. The integrated chip of claim 9 , further comprising:
a second liner layer disposed between the first liner layer and the conductive body, wherein the second liner layer comprises a first lateral segment disposed in the contact region, wherein the first liner layer is offset from the first lateral segment.

14. The integrated chip of claim 13 , wherein a lower surface of the first lateral segment is aligned with or below the lower surface of the first liner layer.

15. The integrated chip of claim 13 , further comprising:
a third liner layer disposed between the second liner layer and the conductive body, wherein the first and second liner layers comprise a first material and the third liner layer comprise a second material different from the first material.

16. The integrated chip of claim 9 , wherein a least a portion of the lower surface of the first liner layer contacts the pair of vertical segments.

17. An integrated chip, comprising:
a dielectric layer over a substrate; and
a conductive interconnect structure disposed in the dielectric layer, wherein the conductive interconnect structure comprises a conductive body, a first liner layer disposed between the conductive body and the dielectric layer, a second liner layer between the first liner layer and the conductive body, wherein when viewed in top view a bottom surface of the first liner layer is ring-shaped and extends around a center region of the conductive interconnect structure, wherein the first liner layer comprises a first material, the second liner layer comprises a second material, and the conductive body comprises a third material, wherein the first material is different from and has a higher resistivity than the second material and the third material.

18. The integrated chip of claim 17 ,
wherein when viewed in a top view a bottom surface of the second liner layer has a circular shape.

19. The integrated chip of claim 18 , wherein a difference in height between the conductive body and the first liner layer is equal to a thickness of the second liner layer along the bottom surface of the conductive body.

20. The integrated chip of claim 17 , further comprising:
a lower conductive interconnect structure under the conductive interconnect structure, wherein the lower conducive interconnect structure comprises a lower conductive body and a capping layer extending along an upper surface of the conductive body, wherein the capping layer comprises the second material, and wherein the first liner layer contacts the capping layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsueh Hsiu-Wen
• Chen Chii-Ping
• Yang Neng-Jye
• Lee Ya-Lien
• Fu An-Jiao
• Tseng Ya-Ching

Classifications

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/47 Primary

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title