Method of manufacturing semiconductor device

US12368068B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12368068-B2
Application numberUS-202117334148-A
CountryUS
Kind codeB2
Filing dateMay 28, 2021
Priority dateJul 14, 2020
Publication dateJul 22, 2025
Grant dateJul 22, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of manufacturing a semiconductor device, including preparing a semiconductor wafer having a first main surface and a second main surface opposite to each other, forming a first electrode on the first main surface of the semiconductor wafer, applying a first tape to the second main surface of the semiconductor wafer, so as to cover the second main surface of the semiconductor wafer with the first tape, applying a second tape to an outer peripheral portion of the semiconductor wafer, to thereby cover an end of the semiconductor wafer with the second tape, heating the semiconductor wafer having the first tape and the second tape applied thereto, by a heat treatment at a temperature of at least 40 degrees C., and forming a plating layer on a surface of the first electrode after heating the semiconductor wafer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor device, comprising: preparing a semiconductor wafer, the semiconductor wafer having a first main surface and a second main surface opposite to each other; forming a first electrode on the first main surface of the semiconductor wafer; applying a first tape to the second main surface of the semiconductor wafer, so as to cover the second main surface of the semiconductor wafer with the first tape; applying a second tape to an outer peripheral portion of the semiconductor wafer, to thereby cover the outer peripheral portion of the semiconductor wafer with the second tape; heating the semiconductor wafer having the first tape and the second tape applied thereto, by a heat treatment that is performed for in a range from 20 minutes to 40 minutes at a temperature of at least 40 degrees C. but less than 60 degrees C.; and forming a plating layer on a surface of the first electrode after heating the semiconductor wafer, wherein the first main surface of the semiconductor wafer in the outer peripheral portion thereof is exposed to an exterior of the semiconductor wafer, and the applying the second tape includes applying the second tape to the outer peripheral portion of the semiconductor wafer in such a way that the second tape is applied directly on the first main surface of the semiconductor wafer at the outer peripheral portion thereof. 2. The method according to claim 1 , wherein the second tape has an adhesive layer that is hardenable by ultraviolet irradiation, to thereby reduce adhesive strength thereof, the second tape extends from the first main surface of the semiconductor wafer to the second main surface of the semiconductor wafer, and the method further includes: applying the ultraviolet irradiation to harden the adhesive layer of the second tape after forming the plating layer; and peeling the second tape from the semiconductor wafer after applying the ultraviolet irradiation. 3. The method according to claim 2 , wherein the second tape is so applied as to extend from the first main surface of the semiconductor wafer to the second main surface of the semiconductor wafer, and to overlap the first tape in the outer peripheral portion of the semiconductor wafer at the second main surface of the semiconductor wafer, and the second tape is peeled after the adhesive layer of the second tape applied to the first main surface of the semiconductor wafer is hardened by the ultraviolet irradiation from the first main surface of the semiconductor wafer. 4. The method according to claim 1 , wherein the second tape is applied to go around the outer peripheral portion of the semiconductor wafer at least one time. 5. The method according to claim 1 , wherein the heating the semiconductor wafer includes inserting the semiconductor wafer in a heating furnace and directly heating the first tape and the second tape. 6. The method according to claim 1 , wherein the heating the semiconductor wafer includes heating a stage by a heating means, and placing the semiconductor wafer on the heated stage, to thereby heat the first tape and the second tape. 7. The method according to claim 5 , wherein the heating the semiconductor wafer includes heating the semiconductor wafer in a nitrogen atmosphere. 8. The method according to claim 6 , wherein the heating the semiconductor wafer includes heating the semiconductor wafer in a nitrogen atmosphere. 9. The method according to claim 1 , further comprising forming a second electrode on the second main surface of the semiconductor wafer, wherein the applying the first tape to the second main surface of the semiconductor wafer includes covering the second electrode with the first tape. 10. The method according to claim 1 , wherein the semiconductor wafer has a center portion surrounded by the outer peripheral portion, and is of a rib-shape in a cross-sectional view thereof, a thickness of the semiconductor wafer being thinner in the center portion thereof than in the outer peripheral portion thereof. 11. The method according to claim 1 , wherein the heating the semiconductor wafer is performed by batch processing in which a plurality of semiconductor wafers are placed in a wafer cassette and the heat treatment is performed correctively on the plurality of semiconductor wafers.

Assignees

Inventors

Classifications

  • Separation by peeling · CPC title

  • H10P14/46Primary

    using a liquid · CPC title

  • Wafer tapes, e.g. grinding or dicing support tapes · CPC title

  • Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

  • using vacuum or suction, e.g. Bernoulli chucks · CPC title

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Frequently asked questions

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What does patent US12368068B2 cover?
A method of manufacturing a semiconductor device, including preparing a semiconductor wafer having a first main surface and a second main surface opposite to each other, forming a first electrode on the first main surface of the semiconductor wafer, applying a first tape to the second main surface of the semiconductor wafer, so as to cover the second main surface of the semiconductor wafer with…
Who is the assignee on this patent?
Fuji Electric Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/46. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 22 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).