Resistive memory cell with switching layer comprising one or more dopants

Patent metadata

Field	Value
Publication number	US-12364171-B2
Application number	US-202418403014-A
Country	US
Kind code	B2
Filing date	Jan 3, 2024
Priority date	Apr 24, 2020
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.

First claim

What is claimed is:

1. An integrated chip, comprising:
a first conductive structure over a substrate;
a data storage structure over the first conductive structure, wherein the data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer, wherein the first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure; and
a second conductive structure on the data storage structure.

2. The integrated chip of claim 1 , wherein an atomic percentage of the first dopant in the second dielectric layer is less than an atomic percentage of the first dopant in the first dielectric layer.

3. The integrated chip of claim 1 , wherein a location of a peak of the concentration of the first dopant in the first dielectric layer is spaced from a bottom surface of the first dielectric layer by a first distance and is spaced from a bottom surface of the second dielectric layer by a second distance less than the first distance.

4. The integrated chip of claim 1 , wherein the first dielectric layer comprises a plurality of intrinsic oxygen vacancies, wherein the intrinsic oxygen vacancies are disposed in the first dielectric layer before performing a forming operation.

5. The integrated chip of claim 1 , wherein the second dielectric layer comprises the dielectric material and is devoid of the first dopant.

6. The integrated chip of claim 1 , further comprising:
a conductive interconnect structure under the first conductive structure; and
an etch stop layer over the conductive interconnect structure, wherein the first conductive structure is disposed in the etch stop layer, wherein the first dielectric layer comprises a middle region over the conductive interconnect structure and a peripheral region over a top surface of the etch stop layer, wherein the middle region of the first dielectric layer extends below the top surface of the etch stop layer.

7. The integrated chip of claim 6 , further comprising:
a sidewall spacer extending from a top surface of the first conductive structure to sidewalls of the first dielectric layer and sidewalls of the second dielectric layer.

8. The integrated chip of claim 1 , wherein a thickness of the first dielectric layer is less than a thickness of the second dielectric layer, wherein a thickness of the first conductive structure is less than a thickness of the second conductive structure.

9. An integrated chip, comprising:
a conductive interconnect structure overlying a substrate; and
a memory cell overlying the conductive interconnect structure, wherein the memory cell comprises a first electrode, a first dielectric layer over the first electrode, a second dielectric layer over the first dielectric layer, and a second electrode over the second dielectric layer, wherein the memory cell is configured to switch between a high resistance state and a low resistance state, wherein the first dielectric layer comprises an intrinsic conductive path disposed in the first dielectric layer in the high resistance state and the low resistance state.

10. The integrated chip of claim 9 , wherein the intrinsic conductive path overlies the conductive interconnect structure and vertically extends from a bottom surface of the first dielectric layer to a top surface of the first dielectric layer.

11. The integrated chip of claim 9 , wherein the first dielectric layer comprises a first dopant configured to form the intrinsic conductive path.

12. The integrated chip of claim 9 , wherein in the low resistance state an upper conductive path is disposed in the second dielectric layer and overlies the intrinsic conductive path.

13. The integrated chip of claim 12 , wherein in the high resistance state at least a portion of the upper conductive path is dissolved.

14. The integrated chip of claim 12 , wherein a width of the upper conductive path is greater than a width of the intrinsic conductive path.

15. The integrated chip of claim 9 , wherein the memory cell further comprises a capping layer disposed between the second electrode and the second dielectric layer, wherein outer sidewalls of the capping layer are aligned with outer sidewalls of the second electrode.

16. The integrated chip of claim 9 , wherein the first dielectric layer is co-doped with a first dopant and a second dopant.

17. An integrated chip, comprising:
a first conductive structure over a substrate;
a second conductive structure over the first conductive structure; and
a data storage structure arranged between the first conductive structure and the second conductive structure, wherein the data storage structure comprises a first dopant, wherein a peak concentration of the first dopant in the data storage structure is above a top surface of the first conductive structure and below a horizontal line intersecting a midpoint of a thickness of the data storage structure.

18. The integrated chip of claim 17 , wherein the peak concentration of the first dopant is vertically offset from the top surface of the first conductive structure by a first distance that is within a range of about 5 to 40 percent of the thickness of the data storage structure.

19. The integrated chip of claim 17 , wherein the data storage structure comprises a first layer on the first conductive structure and a second layer arranged between the first layer and the second conductive structure, wherein a first distance between the peak concentration and the top surface of the first conductive structure is greater than a second distance between the peak concentration and a bottom surface of the second layer.

20. The integrated chip of claim 17 , wherein the data storage structure comprises an intrinsic conductive filament, wherein a first width of the intrinsic conductive filament abutting the top surface of the first conductive structure is less than a second width of the intrinsic conductive filament above the peak concentration.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• JIANG Fa-Shen
• Tsai Cheng-Yuan
• Trinh Hai-Dang
• Lin Hsing-Lien
• Kuang Hsun-Chung
• Lee Bi-Shen

Classifications

• H10N70/8833 Primary

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• H10N70/043

  by implantation · CPC title

• H10N70/24 Primary

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10B63/30

  comprising selection components having three or more electrodes, e.g. transistors · CPC title