Conductive contact for ion through-substrate via

Patent metadata

Field	Value
Publication number	US-12364048-B2
Application number	US-202418429535-A
Country	US
Kind code	B2
Filing date	Feb 1, 2024
Priority date	Aug 29, 2019
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a first substrate having a front-side and a back-side opposite the front-side. A first doped region is in the first substrate and extends continuously from the front-side to the back-side. A conductive contact is over the first doped region. A conductive layer is between the first doped region and the conductive contact. The first doped region abuts a lower surface and sides of the conductive layer.

First claim

What is claimed is:

1. An integrated chip, comprising:
a first substrate comprising a front-side and a back-side opposite the front-side;
a first doped region in the first substrate and extending continuously from the front-side to the back-side;
a conductive contact over the first doped region; and
a conductive layer between the first doped region and the conductive contact, wherein the first doped region abuts a lower surface and sides of the conductive layer.

2. The integrated chip of claim 1 , wherein the first substrate comprises a first material and the conductive contact comprises a second material, wherein the conductive layer comprises the first material and the second material.

3. The integrated chip of claim 1 , wherein the conductive contact comprises a first contact layer over the first doped region, a second contact layer on the first contact layer, and a third contact layer on the second contact layer, wherein the first, second, and third contact layers comprise conductive materials different from one another.

4. The integrated chip of claim 3 , wherein the first contact layer comprises a first metal material, the second contact layer comprises a metal nitride material, and the third contact layer comprises a second metal material.

5. The integrated chip of claim 1 , wherein the conductive layer has an ohmic contact with the first doped region.

6. The integrated chip of claim 1 , further comprising:
an isolation structure in the first substrate and around the first doped region, wherein the conductive layer is spaced between opposing sidewalls of the isolation structure.

7. The integrated chip of claim 1 , further comprising:
an interconnect structure over the first substrate and electrically coupled to the conductive contact;
a second substrate on the interconnect structure; and
a plurality of photodetectors disposed in the second substrate, wherein the plurality of photodetectors comprise a doped photodetector having a first doping type, wherein the first doped region comprises the first doping type.

8. The integrated chip of claim 1 , further comprising:
a second doped region in the first substrate and on opposing sides of the first doped region, wherein the first doped region and the second doped region comprise different doping types, and wherein the first doped region and the second doped region define a through substrate via (TSV).

9. The integrated chip of claim 8 , wherein opposing outer sidewalls of the conductive contact are spaced between opposing sides of the second doped region.

10. An integrated chip, comprising:
a substrate having a height defined between a first surface opposite a second surface;
a first doped region in the substrate and spanning the height of the substrate;
a conductive structure over the first doped region; and
a conductive layer directly between the first doped region and the conductive structure, wherein the conductive layer comprises a silicide.

11. The integrated chip of claim 10 , wherein the conductive layer vertically extends from the second surface of the substrate to a point below the second surface and in a direction of the first surface.

12. The integrated chip of claim 10 , wherein the conductive layer is spaced between outer sidewalls of the conductive structure.

13. The integrated chip of claim 10 , further comprising:
a first interconnect structure on the first surface of the substrate and comprising a plurality of first conductive interconnects electrically coupled to the first doped region; and
a second interconnect structure over the second surface of the substrate and comprising a plurality of second conductive interconnects electrically coupled to the first doped region by way of the conductive structure and the conductive layer.

14. The integrated chip of claim 10 , further comprising:
a second doped region in the substrate and spanning the height of the substrate, wherein the second doped region is laterally offset from the first doped region and has a conductivity type different from that of the first doped region.

15. The integrated chip of claim 14 , wherein the first doped region at least partially defines a first through substrate via (TSV) and the second doped region at least partially defines a second TSV.

16. The integrated chip of claim 10 , further comprising:
a dielectric structure on the second surface of the substrate and comprising sidewalls defining a trench over the first doped region; and
wherein the conductive structure comprises a first layer lining the trench, a second layer on the first layer, and a conductive core over the second layer, wherein the second layer extends along sidewalls and a lower surface of the conductive core, wherein the first layer and the second layer respectively comprise one or more conductive materials.

17. An integrated chip, comprising:
a substrate having a first surface opposite a second surface;
a first doped region in the substrate and traversing a vertical distance from the first surface of the substrate to the second surface of the substrate;
a first conductive structure on the first surface and under the first doped region;
a second conductive structure on the second surface and over the first doped region; and
a conductive layer vertically between the first doped region and the second conductive structure.

18. The integrated chip of claim 17 , wherein a width of the conductive layer is greater than a width of the second conductive structure.

19. The integrated chip of claim 17 , wherein the conductive layer is enclosed by the first doped region and the second conductive structure.

20. The integrated chip of claim 17 , wherein a height of the first doped region is greater than a height of the first conductive structure and a height of the second conductive structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Min-Ying
• Wu Cheng-Ta
• Tu Yeur-Luen

Classifications

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title