Integrated circuit structures having metal gates with tapered plugs

Patent metadata

Field	Value
Publication number	US-12364002-B2
Application number	US-202117359320-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin having a portion protruding above a shallow trench isolation (STI) structure;
a gate dielectric material layer over the protruding portion of the fin and over the STI structure;
a conductive gate layer over the gate dielectric material layer;
a conductive gate fill material over the conductive gate layer; and
a dielectric gate plug laterally spaced apart from the fin, the dielectric gate plug on the STI structure, and the dielectric gate plug having sides tapered outwardly continuous from a top of the dielectric gate plug to a bottom of the dielectric gate plug, wherein a lower portion of the sides are tapered to a greater extend than an upper portion of the sides.

2. The integrated circuit structure of claim 1 , wherein the gate dielectric material layer is a high-k gate dielectric layer.

3. The integrated circuit structure of claim 1 , wherein the conductive gate layer is a workfunction metal layer.

4. The integrated circuit structure of claim 1 , wherein a dielectric gate cap is on the conductive gate fill material.

5. The integrated circuit structure of claim 1 , wherein an oxidized portion of the fin is between the protruding portion of the fin and the gate dielectric material layer.

6. An integrated circuit structure, comprising:
a sub-fin having a portion protruding above a shallow trench isolation (STI) structure;
a plurality of horizontally stacked nanowires over the sub-fin;
a gate dielectric material layer over the protruding portion of the fin, over the STI structure, and surrounding the horizontally stacked nanowires;
a conductive gate layer over the gate dielectric material layer;
a conductive gate fill material over the conductive gate layer; and
a dielectric gate plug laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate plug on the STI structure, and the dielectric gate plug having sides tapered outwardly continuous from a top of the dielectric gate plug to a bottom of the dielectric gate plug, wherein a lower portion of the sides are tapered to a greater extend than an upper portion of the sides.

7. The integrated circuit structure of claim 6 , wherein the gate dielectric material layer is a high-k gate dielectric layer.

8. The integrated circuit structure of claim 6 , wherein the conductive gate layer is a workfunction metal layer.

9. The integrated circuit structure of claim 6 , wherein a dielectric gate cap is on the conductive gate fill material.

10. The integrated circuit structure of claim 6 , wherein an oxidized portion of the sub-fin is between the protruding portion of the sub-fin and the gate dielectric material layer, and an oxidized portion of the horizontally stacked nanowires is between the horizontally stacked nanowires and the gate dielectric material layer.

11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin having a portion protruding above a shallow trench isolation (STI) structure;
a gate dielectric material layer over the protruding portion of the fin and over the STI structure;
a conductive gate layer over the gate dielectric material layer;
a conductive gate fill material over the conductive gate layer; and
a dielectric gate plug laterally spaced apart from the fin, the dielectric gate plug on the STI structure, and the dielectric gate plug having sides tapered outwardly continuous from a top of the dielectric gate plug to a bottom of the dielectric gate plug, wherein a lower portion of the sides are tapered to a greater extend than an upper portion of the sides.

12. The computing device of claim 11 , further comprising:
a memory coupled to the board.

13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

15. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a sub-fin having a portion protruding above a shallow trench isolation (STI) structure;
a plurality of horizontally stacked nanowires over the sub-fin;
a gate dielectric material layer over the protruding portion of the fin, over the STI structure, and surrounding the horizontally stacked nanowires;
a conductive gate layer over the gate dielectric material layer;
a conductive gate fill material over the conductive gate layer; and
a dielectric gate plug laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate plug on the STI structure, and the dielectric gate plug having sides tapered outwardly continuous from a top of the dielectric gate plug to a bottom of the dielectric gate plug, wherein a lower portion of the sides are tapered to a greater extend than an upper portion of the sides.

17. The computing device of claim 16 , further comprising:
a memory coupled to the board.

18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20. The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Hasan Mohammad
• Guha Biswajeet
• Golonzka Oleg
• Guler Leonard P
• Shoer Leah
• Ouellette Daniel G
• Franco Navarro Pedro
• Ghani Tahir

Classifications

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D84/0153

  using gate cut processes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title