Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12363903-B2
Application number	US-202318487553-A
Country	US
Kind code	B2
Filing date	Oct 16, 2023
Priority date	Sep 25, 2020
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate;
forming a plurality of holes that pass through the stack in a vertical direction;
sequentially forming a charge storage layer, a tunnel insulating layer, and a channel layer on sidewalls of each of the plurality of holes;
forming a core insulating layer on a sidewall of the channel layer to fill center regions of the plurality of holes; and
injecting a dopant into a partial region of the core insulating layer so that a dielectric constant of the partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer, the partial region corresponding to a source select transistor or a drain select transistor.

2. The method of claim 1 , further comprising:
removing the plurality of sacrificial layers; and
forming gate electrodes in a space from which the sacrificial layers are removed.

3. The method of claim 2 , wherein at least one first gate electrode that is disposed at a lowermost portion of the gate electrodes and at least one second gate electrode that is disposed at an uppermost portion of the gate electrodes correspond to a select transistor.

4. The method of claim 3 , wherein the partial region is a region of the core insulating layer that is adjacent to the first gate electrode or the second gate electrode.

5. A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate;
forming a plurality of holes that pass through the stack in a vertical direction;
sequentially forming a charge storage layer, a tunnel insulating layer, and a channel layer on sidewalls of each of the plurality of holes; and
forming a core insulating layer on a sidewall of the channel layer to fill a center region of the plurality of holes,
wherein forming the core insulating layer comprises forming a gap in a partial region of the core insulating layer which corresponds to a source select transistor or a drain select transistor, and
wherein a dielectric constant of the partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer which corresponds to memory cells.

6. The method of claim 5 , further comprising:
removing the plurality of sacrificial layers; and
forming gate electrodes in a space from which the sacrificial layers are removed.

7. The method of claim 6 , wherein at least one first gate electrode that is disposed at a lowermost portion of the gate electrodes and at least one second gate electrode that is disposed at an uppermost portion of the gate electrodes correspond to a select transistor.

8. The method of claim 7 , wherein the partial region is a region of the core insulating layer that is adjacent to the first gate electrode or the second gate electrode.

Assignees

• Sk Hynix Inc

Inventors

• Yun dae hwan
• Choi Gil Bok

Classifications

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title