Method for manufacturing semiconductor structure, and semiconductor structure

Patent metadata

Field	Value
Publication number	US-12362192-B2
Application number	US-202117603320-A
Country	US
Kind code	B2
Filing date	Jul 20, 2021
Priority date	Mar 31, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A method for manufacturing a semiconductor structure includes: providing a substrate, a first mask and a second mask, etching the substrate by respectively using the first mask and the second mask, so as to form first grooves and second grooves on the substrate, wherein regions, in the substrate, where the first grooves and the second grooves are located form bit line grooves; and forming a conductive layer in each of the bit line grooves.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, the substrate comprising a plurality of active regions;
providing a first mask, the first mask comprising a plurality of first mask strips extending in a first direction, the plurality of first mask strips being parallel to one another;
using the first mask as a mask, etching the substrate blocked by the first mask strips, so as to form a plurality of first grooves in the substrate;
providing a second mask, the second mask comprising a plurality of second mask strips extending in a second direction, the plurality of second mask strips being parallel to one another, and the first direction intersecting with the second direction;
using the second mask as a mask, etching the substrate blocked by the second mask strips, so as to form a plurality of second grooves in the substrate, wherein regions, of the substrate, where the first grooves and the second grooves are located form bit line grooves, and the bit line grooves expose a part of the active regions; and
forming a conductive layer in each of the bit line grooves;
wherein after forming the conductive layer in each of the bit line grooves, the method further comprises:
forming a first initial dielectric layer on the substrate;
forming a second transfer pattern layer having a pattern on the first initial dielectric layer; and
using the second transfer pattern layer as a mask, etching the first initial dielectric layer, the first initial dielectric layer reserved forming first dielectric layers, each of the first dielectric layers and the conductive layer constituting a bit line; wherein
forming the second transfer pattern layer having the pattern on the first dielectric layer comprises:
providing a third mask, the third mask comprising a plurality of third mask strips arranged at intervals; and
using the third mask as a mask, etching the second transfer pattern layer, so as to pattern the second transfer pattern layer;
using the second transfer pattern layer as the mask, etching the first initial dielectric layer so as to form the bit line comprises:
the projection shape of the bit line is a fold line structure, and the bit line includes a plurality of first bit line structures extending in the second direction and a plurality of second bit line structures extending in the first direction, wherein each of the plurality of first bit line structures and each of the plurality of second bit line structures are arranged alternately, a bit line contact structure is provided at a connection position of each of the plurality of first bit line structures and each of the plurality of second bit line structures, the bit line contact structure is connected to the active regions, and an isolation structure is provided in a region enclosed by adjacent each of the plurality of first bit line structures and each of the plurality of second bit line structures.

2. The method for manufacturing the semiconductor structure according to claim 1 , wherein
an angle between the first direction and the second direction is 10° to 60°.

3. The method for manufacturing the semiconductor structure according to claim 2 , wherein
a region of the substrate except the first grooves and the second grooves constitutes a plurality of isolation structures, the second groove is located between two adjacent isolation structures in the first direction, and the first groove is located between the two adjacent isolation structures in the second direction.

4. The method for manufacturing the semiconductor structure according to claim 3 , wherein
a plane parallel to the substrate is a cross section, a cross section of each of the isolation structures is diamond-shaped.

5. The method for manufacturing the semiconductor structure according to claim 2 ,
wherein providing the substrate comprises:
forming a first transfer pattern layer on the substrate;
using the first mask as the mask comprises:
using the first mask as the mask, etching the first transfer pattern layer blocked by the first mask strips, so as to form a plurality of first intermediate grooves in the first transfer pattern layer, a projection of each of the first intermediate grooves on the substrate coinciding with each of the first grooves; and
using the second mask as the mask comprises:
using the second mask as the mask, etching the first transfer pattern layer blocked by the second mask strips, so as to form a plurality of second intermediate grooves in the first transfer pattern layer, a projection of each of the second intermediate grooves on the substrate coinciding with each of the second grooves.

6. The method for manufacturing the semiconductor structure according to claim 1 ,
wherein providing the substrate comprises:
forming a first transfer pattern layer on the substrate;
using the first mask as the mask comprises:
using the first mask as the mask, etching the first transfer pattern layer blocked by the first mask strips, so as to form a plurality of first intermediate grooves in the first transfer pattern layer, a projection of each of the first intermediate grooves on the substrate coinciding with each of the first grooves; and
using the second mask as the mask comprises:
using the second mask as the mask, etching the first transfer pattern layer blocked by the second mask strips, so as to form a plurality of second intermediate grooves in the first transfer pattern layer, a projection of each of the second intermediate grooves on the substrate coinciding with each of the second grooves.

7. The method for manufacturing the semiconductor structure according to claim 6 , wherein
the first transfer pattern layer comprises a plurality of sub-mask layers provided in a stacked manner, and adjacent sub-mask layers are made of different materials.

8. The method for manufacturing the semiconductor structure according to claim 1 , wherein
after using the second mask as the mask, etching the substrate blocked by the second mask strips, and before forming the conductive layer in each of the bit line grooves, the method further comprises:
forming barrier layers on sidewalls of each of the bit line grooves, the barrier layers being configured to prevent conductive material in the conductive layer from diffusing into the substrate.

9. The method for manufacturing the semiconductor structure according to claim 1 , wherein
the conductive layer comprises a first conductive layer and a second conductive layer which are stacked, and the first conductive layer is provided below the second conductive layer.

10. The method for manufacturing the semiconductor structure according to claim 8 , wherein
the first conductive layer comprises polysilicon, and the second conductive layer comprises tungsten.

11. The method for manufacturing the semiconductor structure according to claim 9 , wherein
forming the conductive layer in each of the bit line grooves comprises:
forming a first initial conductive layer in each of the bit line grooves, the first initial conductive layer extending to outside of each of the bit line grooves and being formed above the substrate;
etching the first initial conductive layer located on the substrate, and reserving a part of the first initial conductive layer in each of the bit line grooves to form the first conductive layer;
forming a second initial conductive layer on the first conductive layer, the second initial conductive layer extending to outside of each of the bit line grooves and being formed above the substrate; and
etching the second initial conductive layer, and reserving the second initial conductive layer located in each of the bit line gr

Assignees

• Changxin Memory Tech Inc
• Changxi Memory Tech Inc

Inventors

• Yu Yexiao
• Liu Zhongming
• Cao Xinman
• Fang Jia
• Zhang Jiayun

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10P50/693 Primary

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10B12/482 Primary

  Bit lines · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/485

  Bit line contacts · CPC title