Anti-fuse address decoding circuit, operation method, and memory

Patent metadata

Field	Value
Publication number	US-12362025-B2
Application number	US-202318166693-A
Country	US
Kind code	B2
Filing date	Feb 9, 2023
Priority date	Apr 2, 2022
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

An anti-fuse address decoding circuit includes: a pre-decoding circuit, configured to decode a programming address of an anti-fuse memory array and output a programming address pre-decoded signal; a level shift circuit, coupled to the pre-decoding circuit, and configured to boost the programming address pre-decoded signal and output a boosted signal; and a programming address decoding circuit, configured to receive the boosted signal, decode the boosted signal and output a programming address signal.

First claim

The invention claimed is:

1. An anti-fuse address decoding circuit, comprising:
a pre-decoding circuit, configured to decode a programming address of an anti-fuse memory array and output a programming address pre-decoded signal;
a level shift circuit, coupled to the pre-decoding circuit, and configured to boost the programming address pre-decoded signal and output a boosted signal; and
a programming address decoding circuit, configured to receive the boosted signal, decode the boosted signal and output a programming address signal; wherein:
the level shift circuit comprises a first level shift circuit and a second level shift circuit;
the first level shift circuit is coupled to the pre-decoding circuit, and is configured to boost the programming address pre-decoded signal and output a first boosted signal; and
the second level shift circuit is coupled to the first level shift circuit, and is configured to boost the first boosted signal and output a second boosted signal.

2. The circuit of claim 1 , wherein:
a voltage level of the first boosted signal comprises a logic low value and a logic high value, and a voltage level of the second boosted signal comprises a logic low value and a logic high value; and
the logic low value of the first boosted signal is less than the logic low value of the second boosted signal, and the logic high value of the first boosted signal is less than the logic high value of the second boosted signal.

3. The circuit of claim 2 , wherein:
a voltage level of the programming address pre-decoded signal comprises a logic low value and a logic high value;
the logic low value and the logic high value of the voltage level of the programming address pre-decoded signal are 0V and 1.2V respectively;
the logic low value and the logic high value of the voltage level of the first boosted signal are 0V and 3V respectively; and
the logic low value of the voltage level of the second boosted signal ranges from 2.5V to 3V, and the logic high value of the voltage level of the second boosted signal ranges from 5V to 6V.

4. The circuit of claim 1 , wherein the programming address decoding circuit comprises:
a word line (WL) address decoding circuit, coupled to the first level shift circuit, and configured to output a WL address signal according to the first boosted signal; and
a programming row address decoding circuit, coupled to the second level shift circuit, and configured to output a programming row address signal according to the second boosted signal.

5. The circuit of claim 4 , wherein:
the programming address comprises row address information and sub-array address information;
the first boosted signal comprises a first row address boosted signal and a first sub-array address boosted signal; and
the second boosted signal comprises a second row address boosted signal and a second sub-array address boosted signal.

6. The circuit of claim 5 , wherein
the WL address decoding circuit comprises a first NAND gate and a first phase inverter;
an input end of the first NAND gate is connected to the first row address boosted signal and the first sub-array address boosted signal, and an output end of the first NAND gate is connected to the first phase inverter; and
an output end of the first phase inverter outputs a WL address signal.

7. The circuit of claim 5 , wherein:
the programming row address decoding circuit comprises a second NAND gate and a second phase inverter;
an input end of the second NAND gate is connected to the second row address boosted signal and the second sub-array address boosted signal, and an output end of the second NAND gate is connected to the second phase inverter; and
an output end of the second phase inverter outputs the programming row address signal.

8. The circuit of claim 6 , wherein:
the first NAND gate comprises a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor; and the first phase inverter comprises a third P-type transistor and a third N-type transistor;
control ends of the first P-type transistor and the first N-type transistor are controlled by the first sub-array address boosted signal, and control ends of the second P-type transistor and the second N-type transistor are controlled by the first row address boosted signal;
first poles of the first P-type transistor, the second P-type transistor and the first N-type transistor are connected at a first node, control ends of the third P-type transistor and the third N-type transistor intersect with each other and are connected at the first node, and first poles of the third P-type transistor and the third N-type transistor are connected to each other and output the WL address signal; and
second poles of the second N-type transistor and the third N-type transistor are connected to a first voltage signal; and second poles of the first P-type transistor, the second P-type transistor and the third P-type transistor are connected to a second voltage signal, wherein the first voltage signal is less than the second voltage signal.

9. The circuit of claim 8 , wherein:
a voltage value of the first voltage signal is 0V, and a voltage value of the second voltage signal is 2.5V.

10. The circuit of claim 7 , wherein:
the second NAND gate comprises a fourth P-type transistor, a fifth P-type transistor, a fourth N-type transistor and a fifth N-type transistor; and the second phase inverter comprises a sixth P-type transistor and a sixth N-type transistor;
control ends of the fourth P-type transistor and the fourth N-type transistor are controlled by the second sub-array address boosted signal, and control ends of the fifth P-type transistor and the fifth N-type transistor are controlled by the second row address boosted signal;
first poles of the fourth P-type transistor, the fifth P-type transistor and the fourth N-type transistor are connected at a second node, control ends of the sixth P-type transistor and the sixth N-type transistor intersect with each other and are connected at the second node, and first poles of the sixth P-type transistor and the sixth N-type transistor are connected to each other and output the programming row address signal; and
second poles of the fifth N-type transistor and the sixth N-type transistor are connected to a third voltage signal; and second poles of the fourth P-type transistor, the fifth P-type transistor and the sixth P-type transistor are connected to a fourth voltage signal, wherein the third voltage signal is less than the fourth voltage signal.

11. The circuit of claim 10 , wherein:
a voltage value of the third voltage signal ranges from 2.5V to 3V; and a voltage value of the fourth voltage signal ranges from 5V to 6V.

12. A memory, comprising an anti-fuse address decoding circuit, wherein the anti-fuse address decoding circuit comprises:
a pre-decoding circuit, configured to decode a programming address of an anti-fuse memory array and output a programming address pre-decoded signal;
a level shift circuit, coupled to the pre-decoding circuit, and configured to boost the programming address pre-decoded signal and output a boosted signal; and
a programming address decoding circuit, configured to receive the boosted signal, decode the boosted signal and output a programming address signal;

wherein:
the level shift circuit comprises a first level shift circuit and a second level shift circuit;
the first level shift circuit is coupled to the pre-decoding circuit, and is configured to boost the programming address pre-decoded signal and output a first boosted signal; and
the second level shift circuit is coupled to the f

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Rumin

Classifications

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G11C8/10

  Decoders · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title