Antifuse memory device and operation method thereof

Patent metadata

Field	Value
Publication number	US-10783976-B2
Application number	US-201916453943-A
Country	US
Kind code	B2
Filing date	Jun 26, 2019
Priority date	Jun 26, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A memory device includes a memory cell array comprising a plurality of antifuse memory cells coupled to a plurality of word lines, a plurality of voltage lines and a plurality of bit lines, and a first decoder suitable for generating a word line driving signal associated with a target memory cell among the plurality of antifuse memory cells in response to a first address, and asserting the word line driving signal at least twice during a program operation.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array comprising a plurality of antifuse memory cells coupled to a plurality of word lines, a plurality of voltage lines, and a plurality of bit lines; and
a first decoder suitable for generating a word line driving signal associated with a target memory cell among the plurality of antifuse memory cells in response to a first address, and asserting the word line driving signal at least twice during a program operation.

2. The memory device of claim 1 , further comprising:
a voltage supply circuit suitable for supplying a program voltage or a read voltage, or both through two or more of the plurality of voltage lines in response to the word line driving signal; and
a word line driving circuit suitable for driving one or more of the plurality of word lines in response to the word line driving signal.

3. The memory device of claim 2 , wherein each of the plurality of antifuse memory cells comprises:
two or more antifuse transistors coupled to the voltage supply circuit through respective two or more voltage lines among the plurality of voltage lines; and
a select transistor coupled to the word line driving circuit through a single word line among the plurality of word lines.

4. The memory device of claim 3 , wherein the two or more antifuse transistors are coupled in parallel between a floating node and a common node, and the select transistor is coupled between the common node and a single bit line among the plurality of bit lines.

5. The memory device of claim 3 , wherein during the program operation, the voltage supply circuit supplies the program voltage to a first voltage line coupled to the target memory cell when the word line driving signal is asserted at a first time.

6. The memory device of claim 5 , wherein during the program operation, the voltage supply circuit supplies the program voltage to a second voltage line coupled to the target memory cell when the word line driving signal is asserted at a second time.

7. The memory device of claim 3 , wherein during the program operation, the word line driving circuit asserts a word line signal transmitted through the word line coupled to the target memory cell whenever the word line driving signal is asserted at least twice.

8. The memory device of claim 2 , further comprising:
a second decoder suitable for generating a bit line select signal associated with the target memory cell among the plurality of antifuse memory cells in response to a second address; and
a sense amplifier circuit suitable for sensing and amplifying data of the target memory cell in response to the bit line select signal.

9. A memory cell comprising:
first and second antifuse transistors coupled in parallel between a floating node and a common node; and
a select transistor coupled between the common node and a bit line,
wherein the select transistor is turned on at first and second times to sequentially program the first and second antifuse transistors during a program operation.

10. The memory cell of claim 9 , wherein the first and second antifuse transistors have gate terminals coupled to first and second voltage lines, respectively, among a plurality of voltage lines.

11. The memory cell of claim 10 , wherein the select transistor has a gate terminal coupled to a given word line among a plurality of word lines.

12. The memory cell of claim 11 , wherein the program operation includes first and second program sub-operations, and
wherein the gate terminal of the first antifuse transistor receives a program voltage through the first voltage line when a word line signal transmitted through the given word line is asserted to have a given voltage at the first time during the first program sub-operation.

13. The memory cell of claim 12 , wherein the gate terminal of the second antifuse transistor receives the program voltage through the second voltage line when the word line signal transmitted through the given word line is asserted to have the given voltage at the second time during the second program sub-operation.

14. A method for operating a memory device, the method comprising:
generating a word line driving signal associated with a target memory cell among a plurality of memory cells in response to a row address, wherein the word line driving signal is asserted at least twice during a program operation, the program operation including first and second programming sub-operations;
performing the first programming sub-operation on the target memory cell in response to the word line driving signal asserted at a first time; and
performing the second programming sub-operation on the target memory cell in response to the word line driving signal asserted at a second time.

15. The operation method of claim 14 , further comprising generating a program voltage in response to a program command during the program operation.

16. The operation method of claim 15 , wherein performing the first programming sub-operation on the target memory cell comprises:
driving a single word line coupled to the target memory cell among a plurality of word lines in response to the word line driving signal asserted at the first time; and
asserting a first voltage line signal to have the program voltage in response to the word line driving signal asserted at the first time and providing the first voltage line signal through a first voltage line coupled to the target memory cell among a plurality of voltage lines.

17. The operation method of claim 16 , wherein performing the second programming sub-operation on the target memory cell comprises:
driving the single word line coupled to the target memory cell among the plurality of word lines in response to the word line driving signal asserted at the second time; and
asserting a second voltage line signal to have the program voltage in response to the word line driving signal asserted at the second time and providing the second voltage line signal through a second voltage line coupled to the target memory cell among the plurality of voltage lines.

18. The operation method of claim 15 , wherein performing the first programming sub-operation on the target memory cell comprises:
turning on a select transistor of the target memory cell in response to the word line driving signal asserted at the first time; and
supplying the program voltage to a first antifuse transistor of the target memory cell in response to the word line driving signal asserted at the first time.

19. The operation method of claim 18 , wherein performing the second programming sub-operation on the target memory cell comprises:
turning on the select transistor of the target memory cell in response to the word line driving signal asserted at the second time; and
supplying the program voltage to a second antifuse transistor of the target memory cell in response to the word line driving signal asserted at the second time.

20. The operation method of claim 19 , wherein the first and second antifuse transistors are coupled in parallel to each other between a floating node and a common node, and the select transistor is coupled between the common node and a single bit line among a plurality of bit lines.

Assignees

• Sk Hynix Inc

Inventors

• Jo Hyeon-Ja

Classifications

• G11C17/08 Primary

  using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence) · CPC title

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/08

  Control thereof · CPC title