Display substrate, manufacturing method therefor, and display apparatus

Patent metadata

Field	Value
Publication number	US-12361891-B2
Application number	US-202118269762-A
Country	US
Kind code	B2
Filing date	Dec 22, 2021
Priority date	Dec 22, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A display substrate is disclosed, including a display area and a non-display area. The non-display area has a gate drive circuit including multiple cascaded shift register units. A shift register unit includes an input control circuit and an output circuit. The input control circuit is electrically connected to a clock signal line group, a first power supply line, a second power supply line and an output circuit, the output circuit is electrically connected to the first power supply line and a second power supply line. The input control circuit at least includes an input circuit and a first control circuit. The clock signal line group, the second power supply line, the input control circuit, the output circuit and the first power supply line are arranged sequentially along a first direction. The input circuit is located between the second power supply line and the first control circuit in the first direction.

First claim

The invention claimed is:

1. A display substrate, comprising a gate drive circuit, and the gate drive circuit comprises a plurality of cascaded shift register units; a shift register unit of the plurality of cascaded shift register units comprises an input control circuit and an output circuit; wherein
the input control circuit is electrically connected to a clock signal line group, a first power supply line, a second power supply line and the output circuit, and the output circuit is electrically connected to the first power supply line and the second power supply line;
the input control circuit at least includes an input circuit and a first control circuit, wherein the input circuit is at least electrically connected to a first node and a second node, and the first control circuit is at least electrically connected to the first node, the second node and a first output control node, and is configured to control a voltage of the first output control node under control of the first node and the second node; the output circuit is electrically connected to the first output control node; and
the clock signal line group, the second power supply line, the input control circuit, the output circuit and the first power supply line are arranged sequentially along a first direction, and the input circuit is located between the second power supply line and the first control circuit in the first direction; wherein
the input control circuit further comprises a second control circuit; wherein
the second control circuit is at least electrically connected to the first node and a second output control node, and is configured to control a voltage of the second output control node under control of the first node;
the output circuit is electrically connected to the second output control node; and
the second control circuit is located between the first control circuit and the output circuit in the first direction and is adjacent to the first control circuit in a second direction, and the first direction intersects with the second direction; wherein
the first control circuit at least comprises a first control sub-circuit; wherein
the first control sub-circuit is electrically connected to an input terminal, a second clock signal line, the second node and the first power supply line, and is configured to transmit a first voltage signal provided by the first power supply line to the second node under control of the input terminal and the second clock signal line; and
the first control sub-circuit is adjacent to the input circuit in the first direction, and is located on a side of the input circuit away from the second power supply line, and the first control sub-circuit is arranged along the first direction.

2. The display substrate according to claim 1 , wherein the input circuit comprises a first input sub-circuit and a second input sub-circuit;
wherein the first input sub-circuit is electrically connected to an input terminal, a first clock signal line and the first node, and the second input sub-circuit is electrically connected to the first clock signal line and the second node; and
the second input sub-circuit is located between the second power supply line and the first input sub-circuit in the first direction.

3. The display substrate according to claim 2 , wherein the first input sub-circuit comprises a first transistor, and the second input sub-circuit comprises a third transistor; and
an active layer of the first transistor extends along the first direction, and an active layer of the third transistor extends along the second direction.

4. The display substrate according to claim 1 ,
wherein the first control sub-circuit comprises a second transistor and a fifth transistor; and
active layers of the second transistor and the fifth transistor both extend along the first direction.

5. The display substrate according to claim 4 , wherein the first control circuit further comprises a second control sub-circuit;
the second control circuit is electrically connected to the second clock signal line, the second node and the first output control node, and is configured to control a voltage of the first output control node under control of the second node and the second clock signal line; and
the second control sub-circuit is located between the second power supply line and the second control circuit in the first direction, and is located on a same side of the input circuit and the first control sub-circuit in the second direction.

6. The display substrate according to claim 5 , wherein the second control sub-circuit at least comprises a sixth transistor, a seventh transistor, and a first capacitor;
wherein the first capacitor is located on a side of the sixth transistor close to the second power supply line in the first direction, and the seventh transistor is located on a side of the sixth transistor away from the second power supply line in the first direction; and
an active layer of the sixth transistor extends along the second direction, and an active layer of the seventh transistor extends along the first direction.

7. The display substrate according to claim 6 , wherein the second control sub-circuit further comprises a twelfth transistor; the twelfth transistor is located on a side of the first capacitor close to the second power supply line in the first direction, and is adjacent to the input circuit in the second direction; and
an active layer of the twelfth transistor extends along the second direction.

8. The display substrate according to claim 5 , wherein the first control circuit further comprises a third control sub-circuit;
wherein the third control sub-circuit is electrically connected to the first power supply line, the first node and the first output control node, and is configured to transmit the first voltage signal provided by the first power supply line to the first output control node under control of the first node, or to provide the first voltage signal to the first node under control of the first output control node; and
the third control sub-circuit is located between the first control sub-circuit and the output circuit in the first direction, and is adjacent to the second control circuit in the second direction.

9. The display substrate according to claim 8 , wherein the third control sub-circuit comprises a fourth transistor, an eighth transistor, and a third capacitor;
the fourth transistor is located between the eighth transistor and the third capacitor in the first direction, the third capacitor is adjacent to the output circuit in the first direction, and the eighth transistor is adjacent to the first control sub-circuit in the first direction; and
active layers of the fourth transistor and the eighth transistor both extend along the second direction.

10. The display substrate according to claim 9 , wherein control electrodes of the fourth transistor and the eighth transistor both extend along the first direction, and the control electrode of the fourth transistor and one of plates of the third capacitor are of an integral structure.

11. The display substrate according to claim 9 , wherein the third control sub-circuit and the first control sub-circuit are electrically connected to the first power supply line through a first power supply connection electrode; and
an orthographic projection of the first power supply connection electrode on a base substrate is overlapped with an orthographic projection of the third capacitor on the base substrate.

12. The display substrate according to claim 11 , wherein the second power supply line is electrically connected to the output circuit through a second power supply connection electrode, the second p

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Qing Haigang
• Xiao Yunsheng
• Wang Miao
• Gu Quanyong

Classifications

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K71/20

  Changing the shape of the active layer in the devices, e.g. patterning · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title