Display panel and display device

Patent metadata

Field	Value
Publication number	US-11568781-B2
Application number	US-202117643557-A
Country	US
Kind code	B2
Filing date	Dec 9, 2021
Priority date	Feb 5, 2021
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A display panel and a display device are provided. The display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, where N 2. A shift register of the N levels of shift registers includes: a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal; a second control unit, configured to receive a first voltage signal and a second voltage signal, and control a signal of a second node in response to the signal of the first node, the first clock signal, and a second clock signal; and a third control unit, configured to receive the first voltage signal and the second voltage signal, and control an output signal in response to the signal of the second node and a signal of the third node.

First claim

What is claimed is:

1. A display panel, comprising a driving circuit, wherein:
the driving circuit includes N levels of shift registers cascaded with each other, wherein N 2; and
a shift register of the N levels of shift registers includes:
a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal;
a second control unit, configured to receive a first voltage signal and a second voltage signal, and control a signal of a second node in response to the signal of the first node, the first clock signal, and a second clock signal; and
a third control unit, configured to receive the first voltage signal and the second voltage signal, and control an output signal in response to the signal of the second node and a signal of a third node, wherein the third node is connected to the first node, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal,
wherein:
the second control unit includes an adjustment unit; and
the adjustment unit is configured to, when the signal of the first node and the signal of the third node are each a low-level signal, and the second clock signal is a low-level signal, maintain the low-level signal of the first node.

2. The display panel according to claim 1 , wherein:
the second control unit include a first sub-control unit, a second sub-control unit and a third sub-control unit;
the first sub-control unit is configured to at least receive the second voltage signal, and control a signal of a fourth node in response to the first clock signal and the signal of the first node;
the second sub-control unit is configured to receive the first voltage signal and a signal of the fourth node, and control the signal of the second node in response to the second clock signal and the signal of the first node; and
the third sub-control unit is connected between the first voltage signal and the first node, and the third sub-control unit includes the adjustment unit.

3. The display panel according to claim 2 , wherein:
the third sub-control unit includes a first transistor, wherein a source of the first transistor is connected to a fifth node, and a drain of the first transistor is connected to the first node, and the fifth node is coupled to the first voltage signal; and
the adjustment unit is configured to control a signal of the fifth node, or to control turn-on and turn-off of the first transistor.

4. The display panel according to claim 3 , wherein:
the adjustment unit is configured to control the first transistor to remain turned-off when the signal of the first node and the signal of the third node are each a low-level signal, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

5. The display panel according to claim 4 , wherein:
the adjustment unit is configured to receive the second clock signal, and control gate potential of the first transistor in response to the signal of the fourth node.

6. The display panel according to claim 5 , wherein:
the adjustment unit includes a second transistor, wherein a gate of the second transistor is connected to the fourth node, a source of the second transistor is configured to receive the second clock signal, and a drain of the second transistor is connected to the gate of the first transistor.

7. The display panel according to claim 6 , wherein:
the fifth node is directly connected to the first voltage signal.

8. The display panel according to claim 7 , wherein:
the third sub-control module includes a third transistor, wherein a source of the third transistor is connected to the first voltage signal, a drain of the third transistor is connected to the fifth node, and a gate of the third transistor is coupled to the fourth node.

9. The display panel according to claim 8 , wherein:
the third sub-control module includes a fourth transistor, wherein a source of the fourth transistor is connected to the fourth node, a gate of the fourth transistor is connected to the second clock signal, and a drain of the fourth transistor is connected to the gate of the third transistor.

10. The display panel according to claim 3 , wherein:
the adjustment unit is configured to, when the signal of the first node and the signal of the third node are each a low-level signal, the first clock signal is a low-level signal, and the second clock signal is a high-level signal, control the fifth node to be disconnected from the first voltage signal.

11. The display panel according to claim 10 , wherein:
the third sub-control module includes a third transistor, wherein a source of the third transistor is connected to the first voltage signal, a drain of the third transistor is connected to the fifth node, and a gate of the third transistor is coupled to the adjustment unit; and
the adjustment unit is configured to receive the signal of the fourth node and control gate potential of the third transistor in response to the second clock signal.

12. The display panel according to claim 11 , wherein:
the adjustment unit includes a fourth transistor, wherein a source of the fourth transistor is connected to the fourth node, a gate of the fourth transistor is connected to the second clock signal, and a drain of the fourth transistor is connected to the gate of the third transistor.

13. The display panel according to claim 3 , wherein:
the adjustment unit is configured to, when the signal of the first node and the signal of the third node are each a low-level signal, and the first clock signal is a high-level signal, control the signal of the fifth node to be a low-level signal.

14. The display panel according to claim 13 , wherein:
the third sub-control module includes a third transistor, wherein a source of the third transistor is connected to the first voltage signal, a drain of the third transistor is connected to the fifth node, and a gate of the third transistor is coupled to the fourth node; and
the adjustment unit is configured to receive the second voltage signal, and control the signal of the fifth node in response to the signal of the fourth node.

15. The display panel according to claim 14 , wherein:
when the signal of the fourth node is a high-level signal, the adjustment unit is turned on; and
when the signal of the fourth node is a low-level signal, the adjustment unit is turned off.

16. The display panel according to claim 14 , wherein:
the adjustment unit includes a fifth transistor, wherein a source of the fifth transistor is connected to the second voltage signal, a drain of the fifth transistor is connected to the fifth node, and a gate of the fifth transistor is connected to the fourth node.

17. The display panel according to claim 16 , wherein:
the first transistor and the third transistor are each a PMOS transistor, and the fifth transistor is an NMOS transistor.

18. The display panel according to claim 2 , wherein:
the first sub-control unit includes a sixth transistor and a seventh transistor; and
the second sub-control unit includes an eighth transistor, a ninth transistor, a tenth transistor, and a first capacitor,
wherein:
a source of the sixth transistor is connected to the second voltage signal, a drain of the sixth transistor is connected to the fourth node, and a gate of the sixth transistor is connected to the first clock signal;
a source of the seventh transistor is connected to the first clock signal, a drain of the seventh transistor is connected to the fourth node, and a gate of the seventh

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Lai Qingjun
• Zhu Yihua
• Yuan Yong
• An Ping
• Cao Zhaokeng

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title