Credit aware central arbitration for multi-endpoint, multi-core system

Patent metadata

Field	Value
Publication number	US-12360844-B2
Application number	US-202217875424-A
Country	US
Kind code	B2
Filing date	Jul 28, 2022
Priority date	Oct 15, 2018
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

First claim

What is claimed is:

1. A device comprising:
a resource associated with a number of available credits;
a data path coupled to the resource;
a cache configuration register configured to store a setting; and
an arbiter circuit, wherein the arbiter circuit is configured to:
receive a first memory access request to the resource, the first memory access request associated with a first credit cost;
receive a second memory access request to the resource, the second memory access request associated with a second credit cost;
compare the first credit cost to the number of available credits to determine a first result;
compare the second credit cost to the number of available credits to determine a second result;
based on the first result and the second result, select a pre-arbitration winner between the first memory access request and the second memory access request;
determine whether 1) the setting stored in the cache configuration register has a first value indicative that the pre-arbitration winner is a real-time request or 2) the setting stored in the cache configuration register has a second value indicative that the pre-arbitration winner is a non-real-time request;
determine a first priority of the pre-arbitration winner based on the determination that the setting stored in the cache configuration register has the first value or the second value and a number of real-time requests that have previously been selected;
after receiving the first and second memory access requests, receive a subsequent memory access request to the resource;
compare the first priority with a second priority of the subsequent memory access request to determine a third result;
determine a final arbitration winner based on the third result; and
drive the final arbitration winner to the data path.

2. The device of claim 1 , wherein:
the cache configuration register is configured to store the setting as a bit mask indicating that the pre-arbitration winner is the real-time request or the non-real-time request; and
the first priority is based on a source of the pre-arbitration winner and the bit mask stored in the cache configuration register.

3. The device of claim 1 , wherein:
the first priority is based on a first indicator in the first memory access request or a second indicator in the second memory access request.

4. The device of claim 1 , wherein:
the first result indicates the first credit cost is less than or equal to the number of available credits; and
the second result indicates the second credit cost is less than or equal to the number of available credits.

5. The device of claim 1 , wherein:
the arbiter circuit is configured to:
based on the first and second results, drive the first memory access request to the data path prior to driving the second memory access request to the data path; and
in response to the first credit cost being less than or equal to the number of available credits, decrement the number of available credits by the first credit cost to produce a reduced number of available credits.

6. The device of claim 5 , wherein:
the arbiter circuit is configured to:
drive the second memory access request to the data path subsequent to driving the first memory access request to the data path and prior to receiving an acknowledgement that the first memory access request has been processed by the resource; and
in response to the second credit cost being less than or equal to the reduced number of available credits, decrement the reduced number of available credits by the second credit cost.

7. The device of claim 1 , wherein:
the arbiter circuit is configured to increase the number of available credits to the resource by a first amount equal to the first credit cost in response to receiving an acknowledgement that the first memory access request has been processed by the resource; and
the arbiter circuit is configured to increase the number of available credits to the resource by a second amount equal to the second credit cost in response to receiving an acknowledgement that the second memory access request has been processed by the resource.

8. The device of claim 1 , wherein:
the first memory access request is associated with a first priority group;
the second memory access request is associated with a second priority group; and
the first priority group is associated with a higher priority than the second priority group.

9. The device of claim 8 , wherein:
the arbiter circuit is configured to promote the second memory access request to the first priority group in response to the second memory access request losing arbitration to the first priority group for a number of clock cycles set in a starvation register.

10. The device of claim 1 , wherein:
the number of available credits corresponds to available space in one or more queues of the resource.

11. A method comprising:
receiving, at an arbiter circuit, a first memory access request to a resource coupled to a data path, the first memory access request associated with a first credit cost, wherein the resource includes a number of available credits;
receiving, at the arbiter circuit, a second memory access request to the resource, the second memory access request associated with a second credit cost;
comparing, by the arbiter circuit, the first credit cost to the number of available credits to determine a first result;
comparing, by the arbiter circuit, the second credit cost to the number of available credits to determine a second result;
based on the first result and the second result, selecting, by the arbiter circuit, a pre-arbitration winner between the first memory access request and the second memory access request;
determining whether 1) a setting stored in a cache configuration register has a first value indicative that the pre-arbitration winner is a real-time request or 2) the setting stored in the cache configuration register has a second value indicative that the pre-arbitration winner is a non-real-time request;
determining, by the arbiter circuit, a first priority of the pre-arbitration winner based on the determination that the setting stored in the cache configuration register has the first value or the second value and a number of real-time requests that have previously been selected;
after receiving the first and second memory access requests, receiving, by the arbiter circuit, a subsequent memory access request to the resource;
comparing, by the arbiter circuit, the first priority with a second priority of the subsequent memory access request to determine a third result;
determining, by the arbiter circuit, a final arbitration winner based on the third result; and
driving, by the arbiter circuit, the final arbitration winner to the data path based.

12. The method of claim 11 , wherein:
the setting is stored in the cache configuration register as a bit mask indicating that the pre-arbitration winner is the real-time request or the non-real-time request; and
the first priority is based on a source of the pre-arbitration winner and the bit mask stored in the cache configuration register.

13. The method of claim 11 , wherein:
the first priority is based on a first indicator in the first memory access request or a second indicator in the second memory access request.

14. The method of claim 11 , wherein:
the first result indicates the first credit cost is less than or equal to the number of available credits; and
the second result indicates the second credit cost is less than or equal to the number of available credits.

15. The method of claim 11 , further comprising:
based on th

Assignees

• Texas Instruments Inc

Inventors

• Pierson Matthew David
• Chirca Kai
• Wu Daniel

Classifications

• G06F12/0862

  with prefetch · CPC title

• G06F12/0851

  Cache with interleaved addressing · CPC title

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F2212/6024

  History based prefetching · CPC title

• G06F2212/1048

  Scalability · CPC title