Capacitor, memory device including the capacitor

US12356643B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12356643-B2
Application numberUS-202217715473-A
CountryUS
Kind codeB2
Filing dateApr 7, 2022
Priority dateSep 28, 2021
Publication dateJul 8, 2025
Grant dateJul 8, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A capacitor includes a lower electrode layer including a first conductive layer and a second conductive layer on the first conductive layer, the second conductive layer including SnO2 doped with an impurity; a dielectric layer on the second conductive layer, the dielectric layer including a rutile-phase oxide; and an upper electrode layer on the dielectric layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A capacitor comprising: a lower electrode layer including a first conductive layer and a second conductive layer on the first conductive layer, the second conductive layer including SnO 2 doped with an impurity; a dielectric layer on the second conductive layer, the dielectric layer including a rutile-phase oxide; and an upper electrode layer on the dielectric layer, wherein the impurity of the second conductive layer comprises at least one of niobium (Nb), or manganese (Mn), and wherein a doping concentration of the impurity with respect to the second conductive layer is included in a range from 0.5 at % to 10 at %. 2. The capacitor of claim 1 , wherein a work function of the second conductive layer is included in a range from 4.3 eV to 5 eV. 3. The capacitor of claim 1 , wherein a thickness of the second conductive layer is included in a range from 1 nm to 100 nm. 4. The capacitor of claim 1 , wherein a resistivity of the second conductive layer is included in a range from 10 μΩcm to 4000 μΩcm. 5. The capacitor of claim 1 , wherein a sum of a thickness of the first conductive layer and a thickness of the second conductive layer is less than 10 nm. 6. The capacitor of claim 1 , wherein a permittivity of the dielectric layer is included in a range from 60 to 100. 7. The capacitor of claim 1 , wherein the rutile-phase oxide comprises titanium dioxide (TiO 2 ). 8. The capacitor of claim 1 , wherein the rutile-phase oxide comprises titanium dioxide (TiO 2 ), and the dielectric layer includes a dopant, the dopant comprising at least one of aluminum (Al), gallium (Ga), germanium (Ge), lanthanum (La), or yttrium (Y). 9. The capacitor of claim 1 , wherein the first conductive layer comprises titanium nitride (TiN). 10. The capacitor of claim 1 , wherein the first conductive layer comprises titanium nitride (TiN) doped with at least one of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), platinum (Pt), rubidium (Ru), or iridium (Ir). 11. A memory device comprising: a transistor including a source region and a drain region spaced apart from each other, a channel region between the source region and the drain region, and a gate electrode on the channel region; a capacitor comprising a lower electrode layer including a first conductive layer and a second conductive layer on the first conductive layer, the second conductive layer including SnO 2 doped with an impurity, a dielectric layer on the second conductive layer, the dielectric layer including a rutile-phase oxide, and an upper electrode on the dielectric layer; and a contact plug electrically connecting the first conductive layer of the lower electrode to at least one of the drain region or the source region, wherein the impurity of the second conductive layer comprises at least one of niobium (Nb), or manganese (Mn), and wherein a doping concentration of the impurity with respect to the second conductive layer is included in a range from 0.5 at % to 10 at %. 12. The memory device of claim 11 , wherein the first conductive layer comprises titanium nitride (TiN).

Assignees

Inventors

Classifications

  • having a storage electrode stacked over the transistor · CPC title

  • Atomic layer deposition [ALD] · CPC title

  • of refractory metals or yttrium · CPC title

  • with the capacitor higher than a bit line · CPC title

  • the capacitor extending over the transistor · CPC title

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What does patent US12356643B2 cover?
A capacitor includes a lower electrode layer including a first conductive layer and a second conductive layer on the first conductive layer, the second conductive layer including SnO2 doped with an impurity; a dielectric layer on the second conductive layer, the dielectric layer including a rutile-phase oxide; and an upper electrode layer on the dielectric layer.
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D1/696. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 08 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).