In-memory computation system with built-in subtraction mode for handling matrix vector multiplication of signed feature data and signed computational weight data

Patent metadata

Field	Value
Publication number	US-12355443-B2
Application number	US-202318241813-A
Country	US
Kind code	B2
Filing date	Sep 1, 2023
Priority date	Sep 1, 2023
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

First claim

The invention claimed is:

1. An in-memory computation circuit, comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, wherein groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration producing a first analog signal and a second MAC elaboration producing a second analog signal; and
an analog-to-digital converter circuit configured to:
increment a count value in a counter circuit in response to the first analog signal;
convert the count value in the counter circuit to a negated count value; and
increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

2. The in-memory computation circuit of claim 1 , wherein the analog-to-digital converter circuit comprises:
an integration circuit configured to integrate the first analog signal to produce a first series of pulses, with the counter circuit incrementing the count value in response to each pulse in the first series; and
wherein the integration circuit is further configured to integrate the second analog signal to produce a second series of pulses, with the counter circuit incrementing the count value starting from the negated count value in response to each pulse of the second series.

3. The in-memory computation circuit of claim 1 , wherein the first MAC elaboration is a negative elaboration and the second MAC elaboration is a positive elaboration; and wherein conversion of the count value in the counter circuit to the negated count value is performed through use of a 2's complement operation on the count value.

4. The in-memory computation circuit of claim 1 :
wherein memory cells in each of first ones of the columns of the memory array are connected by a negative elaboration bit line;
wherein the first analog signal is generated on each negative elaboration bit line during the first MAC elaboration of the in-memory compute operation;
wherein memory cells in each of second ones of the columns of the memory array are connected by a positive elaboration bit line; and
wherein the second analog signal is generated on each positive elaboration bit line during the second MAC elaboration of the in-memory compute operation.

5. The in-memory computation circuit of claim 4 , wherein the analog-to-digital converter circuit includes a column selection circuit configured to select the first analog signal generated on the negative elaboration bit line during the first MAC elaboration and select the second analog signal generated on the positive elaboration bit line during the second MAC elaboration.

6. The in-memory computation circuit of claim 4 , wherein each group of memory cells storing a computational weight comprises four memory cells arranged in a 2×2 matrix with first and second memory cells in the 2×2 matrix of the group connected to the negative elaboration bit line and third and fourth memory cells in the 2×2 matrix of the group connected to the positive elaboration bit line.

7. The in-memory computation circuit of claim 6 , wherein a computational weight of −1 is represented by a matrix

[

0

1

1

0

]

,

a computational weight of 0 is represented by a matrix

[

0

0

0

0

]

,

and a computational weight of +1 is represented by a matrix

[

1

0

0

1

]

.

8. The in-memory computation circuit of claim 6 :
wherein first and third memory cells in the 2×2 matrix of the group are connected to a positive word line actuated during the in-memory compute operation in response to positive feature data; and
wherein second and fourth memory cells in the 2×2 matrix of the group are connected to a negative word line actuated during the in-memory compute operation in response to negative feature data.

9. The in-memory computation circuit of claim 5 :
wherein memory cells in each column of the memory array are connected by a bit line;
wherein the first analog signal is generated on each bit line during the first MAC elaboration of the in-memory compute operation; and
wherein the second analog signal is generated on each bit line during the second MAC elaboration of the in-memory compute operation.

10. The in-memory computation circuit of claim 9 , wherein each group of memory cells storing a computational weight comprises two memory cells arranged in a 1×2 matrix with first and second memory cells in the 1×2 matrix of the group connected to the bit line.

11. The in-memory computation circuit of claim 10 , wherein a computational weight of −1 is represented by a matrix

[

0

1

]

,

a computational weight of 0 is represented by a matrix

[

0

0

]

,

and a computational weight of +1 which is represented by a matrix

[

1

0

]

.

Assignees

• St Microelectronics Int Nv

Inventors

• Pasotti Marco
• Zurla Riccardo
• Carissimi Marcella
• Vignali Riccardo
• Cabrini Alessandro

Classifications

• H03K23/40

  Gating or clocking signals applied to all stages, i.e. synchronous counters {(H03K23/74 - H03K23/84 take precedence)} · CPC title

• G06F2207/4814

  Non-logic devices, e.g. operational amplifiers · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• H03K21/023 Primary

  comprising pulse shaping or differentiating circuits · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title