Variable gain amplifier with cross-coupled common mode reduction

Patent metadata

Field	Value
Publication number	US-12355409-B2
Application number	US-202217702884-A
Country	US
Kind code	B2
Filing date	Mar 24, 2022
Priority date	Mar 24, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Methods and systems for receiving a differential input voltage signal at an input of a variable gain amplifier, and responsively generating an amplified differential output voltage signal on a pair of output nodes by driving a pair of load impedances connected to the pair of output nodes with an amplifier current according to the differential input voltage signal, enabling a cross-coupled differential pair connected in parallel to the pair of load impedances, the cross-coupled differential pair having drain inputs and cross-coupled gate inputs connected to the pair of output nodes to supplement a gain of the amplified differential voltage output voltage signal, and reducing a common mode voltage of the amplified differential output voltage signal by lowering the amplifier current driving the pair of load impedances via a bias control signal, the amplifier current lowered responsive to detecting the supplemented gain of the amplified differential output voltage signal.

First claim

I claim:

1. A method comprising:
receiving a differential input voltage signal at an input of a variable gain amplifier (VGA), and responsively generating an amplified differential output voltage signal on a pair of output nodes by driving a pair of load impedances connected to the pair of output nodes with an amplifier current according to the differential input voltage signal;
receiving a gain control signal at the VGA;
enabling, responsive to a determination that the gain control signal is associated with a predetermined range of gain settings, a cross-coupled differential pair connected in parallel to the pair of load impedances, the cross-coupled differential pair having drain inputs and cross-coupled gate inputs connected to the pair of output nodes to supplement a gain of the amplified differential voltage output voltage signal; and
reducing a common mode voltage of the amplified differential output voltage signal by lowering the amplifier current driving the pair of load impedances via a bias control signal, the amplifier current lowered responsive to detecting the supplemented gain of the amplified differential output voltage signal.

2. The method of claim 1 , wherein the supplemented gain of the amplified differential voltage output voltage signal is adjustable via a cross-coupling voltage control signal, and wherein the cross-coupling voltage control signal is selected based on the gain control signal.

3. The method of claim 1 , further comprising measuring the common mode voltage of the amplified differential output signal, and comparing the common mode voltage to a threshold voltage to control an amount of the supplemented gain.

4. The method of claim 3 , wherein the threshold voltage is adjustable.

5. The method of claim 3 , wherein the threshold voltage is obtained via an external digital loop.

6. The method of claim 5 , wherein the threshold voltage is obtained by comparing the common mode voltage of the amplified differential output signal to a common mode voltage of a decision feedback equalization circuit.

7. The method of claim 1 , wherein detecting the supplemented gain of the amplified differential output signal comprises comparing a differential output voltage of a replica variable gain amplifier against a target differential output voltage.

8. The method of claim 7 , wherein the bias control signal is generated from the comparison of the differential output voltage of the replica variable gain amplifier against the target differential output voltage.

9. The method of claim 8 , wherein the target differential output voltage is obtained from a resistor ladder.

10. An apparatus comprising:
a variable gain amplifier (VGA) configured to receive a differential input voltage signal at an input, and to responsively generate an amplified differential output voltage signal on a pair of output nodes by driving a pair of load impedances connected to the pair of output nodes with an amplifier current according to the differential input voltage signal, the VGA further configured to receive a gain control signal;
a cross-coupled differential pair connected in parallel to the pair of load impedances, the cross-coupled differential pair having drain inputs and cross-coupled gate inputs connected to the pair of output nodes to supplement a gain of the amplified differential voltage output voltage signal, the cross-coupled differential pair selectively enabled to reduce a common mode voltage of the amplified differential output voltage signal by lowering the amplifier current driving the pair of load impedances via a bias control signal, the amplifier current lowered responsive to detecting the supplemented gain of the amplified differential output voltage signal, the cross-coupled differential pair enabled responsive to a determination that the gain control signal is associated with a predetermined range of gain settings.

11. The apparatus of claim 10 , wherein the supplemented gain of the amplified differential voltage output voltage signal is adjustable via a cross-coupling voltage control signal, and wherein the control signal is selected based on the gain control signal.

12. The apparatus of claim 10 , further comprising a cross-coupling voltage control signal generator configured to measure the common mode voltage of the amplified differential output signal, and to compare the common mode voltage to a threshold voltage to control an amount of the supplemented gain.

13. The apparatus of claim 12 , wherein the threshold voltage is adjustable.

14. The apparatus of claim 12 , wherein the threshold voltage is obtained via an external digital loop.

15. The apparatus of claim 14 , wherein the threshold voltage is obtained by comparing the common mode voltage of the amplified differential output signal to a common mode voltage of a decision feedback equalization circuit.

16. The apparatus of claim 10 , further comprising:
a replica VGA configured to generate a differential output voltage based on a replica bias control signal;
a voltage generator configured to generate a variable target differential output voltage; and
a replica bias control signal generator configured to detect the supplemented gain of the amplified differential output signal by forming a comparison of the differential output voltage of the replica VGA to the target differential output voltage, and to responsively generate the replica bias control signal from the comparison of the differential output voltage of the replica VGA to the target differential output voltage.

17. The apparatus of claim 16 , wherein the replica VGA is configured to the generate the differential output voltage based further on a differential reference voltage, the differential reference voltage selected from the voltage generator.

18. The apparatus of claim 16 , wherein the voltage generator is a resistor ladder.

Assignees

• Kandou Labs SA

Inventors

• Fuhs Maik

Classifications

• H03D7/1458

  Double balanced arrangements, i.e. where both input signals are differential · CPC title

• H04L25/03146

  with a recursive structure (H04L25/03127 takes precedence) · CPC title

• H03F2203/45506

  the CSC comprising only one switch · CPC title

• H03G1/0029

  using field-effect transistors [FET] · CPC title

• H03F3/45744

  by offset reduction · CPC title