Differential comparator circuit having a wide common mode input range

Patent metadata

Field	Value
Publication number	US-9178503-B2
Application number	US-79042510-A
Country	US
Kind code	B2
Filing date	May 28, 2010
Priority date	May 28, 2010
Publication date	Nov 3, 2015
Grant date	Nov 3, 2015

Abstract

In one embodiment of the invention, a circuit arrangement is provided. The circuit arrangement includes a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier. Each differential amplifier includes an adjustable current control circuit coupled to limit a tail current passing through the differential amplifier.

First claim

What is claimed is:

1. A circuit arrangement, comprising:
a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier;
for each differential amplifier, a respective adjustable current control circuit coupled to the differential amplifier to limit a tail current passing through the differential amplifier, the adjustable current control circuit being configured to operate in one state of a discrete set of states including fully-on, fully-off, and partially-on, wherein operation of the adjustable current control circuit in the partially-on state causes the differential amplifier to exhibit non-linearity; and
a gain control circuit coupled to the adjustable current control circuits, the gain control circuit configured to adjust, while the adjustable current control circuits for two or more of the plurality of differential amplifiers are operated in respective states other than the fully-off state, the adjustable current control circuits such that only one of the plurality of respective current control circuits can be operated in the partially-on state at a given time, thereby limiting non-linearity exhibited by the plurality of differential amplifiers.

2. The circuit arrangement of claim 1 , wherein:
the gain control circuit is further configured to adjust, in response to a trim control signal indicating the tail current is to be increased, one or more of the adjustable current control circuits to increase the tail currents passing through the respective differential amplifiers; and
the gain control circuit is further configured to adjust, in response to the trim control signal indicating the tail current is to be decreased, one or more of the adjustable current control circuits to decrease the tail currents passing through the respective differential amplifiers.

3. The circuit arrangement of claim 1 , wherein the adjustable current control circuits are adjustable to a plurality of discrete current levels while operating in the partially-on state.

4. The circuit arrangement of claim 1 , wherein each differential amplifier of the plurality of differential amplifiers includes two complementary differential transistor pairs.

5. The circuit arrangement of claim 4 , further comprising a current summation circuit coupled to first and second current outputs of each of the differential transistor pairs of the plurality of the differential amplifiers.

6. The circuit arrangement of claim 1 , wherein the adjustable current control circuits are adjustable current sources.

7. The circuit arrangement of claim 1 , wherein the adjustable current control circuits are MOSFET transistors.

8. The circuit arrangement of claim 7 , wherein gate dimensions of the MOSFET transistors are substantially identical.

9. The circuit arrangement of claim 4 , wherein gate dimensions of the complementary differential transistor pairs in each differential amplifier are substantially identical.

10. A differential comparator circuit having a wideband common mode input range, comprising:
first and second differential input terminals for receiving first and second input signals respectively, a difference between the input signals providing a differential input signal;
a plurality of complementary differential pair circuits having inputs coupled to the first and second differential input terminals and each pair having first, second, third, and fourth outputs, the plurality of complementary differential pair circuits including at least first and second complementary differential transistor pair circuits, respectively;
a current summation circuit coupled to the first, second, third, and fourth current outputs of the complementary differential pair circuits;
a gain control circuit coupled to the complementary differential pair circuits and configured to independently adjust a tail current of each of the plurality of complementary differential transistor pair circuits;
wherein the plurality of complementary differential pair circuits are configurable, via the adjustment of the tail currents, to operate in one state of a discrete set of states consisting of fully-on, fully-off, and partially-on; and
wherein the gain control circuit is configured to adjust the tail currents such that while two or more of the plurality of complementary differential pair circuits are operated in respective states other than the fully-off state, only one of the plurality of complementary differential pair circuits is operated in the partially-on state at a given time.

11. The differential comparator circuit of claim 10 , wherein:
each of the complementary differential pair circuits includes an NMOS differential pair and a PMOS differential pair having overlapping common mode input ranges; and
the gain control circuit is configured to decrease the gain of the differential comparator circuit, via adjustment of the tail currents, in response to the differential comparator circuit operating within the overlapping common mode input ranges.

12. The differential comparator circuit of claim 10 , wherein the gain control circuit is configured to adjust the tail current of each of the plurality of complementary differential transistor pair circuits by adjusting a current control circuit included in each of the plurality of complementary differential transistor pair circuits.

13. The differential comparator circuit of claim 12 , wherein the adjustable current control circuits are adjustable current sources.

14. The differential comparator circuit of claim 12 , wherein the adjustable current control circuits are MOSFET transistors.

15. The differential comparator circuit of claim 14 , wherein gate dimensions of the MOSFET transistors are substantially identical.

16. An input buffer circuit, comprising:
a first electrostatic discharge circuit having inputs for receiving a differential signal from a transmission medium;
termination resistors coupled to differential outputs of the first electrostatic discharge circuit and configured to match the impedance of the input buffer to the impedance of the transmission medium;
a differential comparator circuit coupled to differential output of the termination resistors, the differential comparator circuit including two or more complementary differential pair circuits coupled in parallel;
a current summation circuit coupled to outputs of the two or more complementary differential pair circuits; and
a gain control circuit coupled and configured to independently adjust a tail current of each of the two or more complementary differential pair circuits such that while two or more of the plurality of complementary differential pair circuits are operated in respective states other than the fully-off state, only one of the plurality of plurality of complementary differential pair circuits is operated in the partially-on state at a given time.

17. The input buffer circuit of claim 16 , further comprising a second electrostatic discharge circuit coupled between the termination resistors and the differential comparator circuit.

Assignees

• Hsieh Cheng-Hsiang
• Xilinx Inc

Inventors

• Hsieh Cheng-Hsiang

Classifications

• H03F3/4521

  Complementary long tailed pairs having parallel inputs and being supplied in parallel · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03K5/24 Primary

  the characteristic being amplitude · CPC title