Self-aligned dielectric liner structure for protection in MEMS comb actuator

Patent metadata

Field	Value
Publication number	US-12355370-B2
Application number	US-202217842101-A
Country	US
Kind code	B2
Filing date	Jun 16, 2022
Priority date	Aug 30, 2019
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

In some embodiments, the present disclosure relates to a microelectromechanical system (MEMS) comb actuator including a comb structure. The comb structure includes a support layer having a first material and a plurality of protrusions extending away from a first surface of the support layer in a first direction. The plurality of protrusions are also made of the first material. The plurality of protrusions are separated along a second direction parallel to the first surface of the support layer. The MEMS comb actuator may further include a dielectric liner structure that continuously and completely covers the first surface of the support layer and outer surfaces of the plurality of protrusions. The dielectric liner structure includes a connective portion that continuously connects topmost surfaces of at least two of the plurality of protrusions.

First claim

What is claimed is:

1. A method of forming a comb structure comprising:
forming trench structures in a substrate extending from a topmost surface of the substrate towards a bottommost surface of the substrate;
forming a first dielectric layer over the topmost surface of the substrate, wherein the first dielectric layer covers inner surfaces of the trench structures defined by inner surfaces of the substrate;
forming a semiconductor material over the first dielectric layer;
removing upper portions of the semiconductor material to form the comb structure comprising protrusions within the trench structures;
forming a second dielectric layer over the comb structure;
performing a planarization process to remove portions of the first and/or second dielectric layers to expose the topmost surface of the substrate;
forming a third dielectric layer over the second dielectric layer and/or the topmost surface of the substrate;
patterning the third dielectric layer to remove portions of the third dielectric layer from the topmost surface of the substrate; and
removing portions of the substrate.

2. The method of claim 1 , wherein patterning the third dielectric layer comprises:
forming a masking structure directly over at least two of the protrusions;
performing an etching process to remove portions of the third dielectric layer arranged over the topmost surface of the substrate, wherein the portions of the third dielectric layer are not covered by the masking structure; and
removing the masking structure.

3. The method of claim 2 , wherein after the performing of the etching process, topmost surfaces of the first dielectric layer, the second dielectric layer, and the third dielectric layer that are not directly below the masking structure do not extend above the topmost surface of the substrate.

4. The method of claim 1 , wherein the forming of the second dielectric layer comprises a thermal oxidation process.

5. The method of claim 1 , wherein the forming of the second dielectric layer comprises a chemical vapor deposition process.

6. The method of claim 1 , wherein after removing upper portions of the semiconductor material, topmost surfaces of the protrusions are below the topmost surface of the substrate.

7. The method of claim 1 , wherein the first, second, and third dielectric layers comprise the same material as one another.

8. A method, comprising:
receiving a substrate;
forming a plurality of trenches in the substrate, the trenches extending from an upper surface of the substrate towards a lower surface of the substrate;
forming a first dielectric layer over the upper surface of the substrate and along inner sidewalls of the plurality of trenches;
forming a semiconductor material over the first dielectric layer, the semiconductor material filling the trenches; and
removing upper portions of the semiconductor material to expose the first dielectric layer while leaving lower portions of the semiconductor material in the plurality of trenches, wherein the lower portions of the semiconductor material left in the trenches establish a comb structure.

9. The method of claim 8 , further comprising:
performing an etch to remove portions of the substrate to expose the first dielectric layer, wherein the etch leaves the first dielectric layer covering the comb structure.

10. The method of claim 8 , further comprising:
forming a second dielectric layer over the comb structure; and
performing a planarization process to remove portions of the first dielectric layer and/or the second dielectric layer to expose the upper surface of the substrate.

11. The method of claim 10 , wherein the forming of the second dielectric layer comprises a thermal oxidation process.

12. The method of claim 10 , wherein the forming of the second dielectric layer comprises a chemical vapor deposition process.

13. The method of claim 10 , further comprising:
performing an etch to remove portions of the substrate to expose the first dielectric layer, wherein the etch leaves the first dielectric layer covering the comb structure.

14. The method of claim 10 , further comprising:
forming a third dielectric layer over the second dielectric layer and/or the upper surface of the substrate; and
patterning the third dielectric layer to remove portions of the third dielectric layer from the upper surface of the substrate.

15. The method of claim 14 , wherein the first, second, and third dielectric layers comprise the same material as one another.

16. The method of claim 14 , further comprising:
performing an etch to remove portions of the substrate to expose the first dielectric layer, wherein the etch leaves the first dielectric layer covering the comb structure.

17. A method, comprising:
receiving a substrate;
forming a plurality of trenches in the substrate, the trenches extending from an upper surface of the substrate towards a lower surface of the substrate;
forming a first dielectric layer over the upper surface of the substrate and along inner sidewalls of the plurality of trenches;
forming a semiconductor material over the first dielectric layer, the semiconductor material filling the trenches;
removing upper portions of the semiconductor material to expose the first dielectric layer and leave lower portions of the semiconductor material in the plurality of trenches, the lower portions of the semiconductor material establishing a comb structure including a shaft and a plurality of teeth extending from the shaft; and
performing an etch to remove portions of the substrate to expose the first dielectric layer, wherein the etch leaves the first dielectric layer covering the shaft and the teeth of the comb structure.

18. The method of claim 17 , further comprising:
forming a second dielectric layer over the comb structure; and
performing a planarization process to remove portions of the first dielectric layer and/or the second dielectric layer to expose the upper surface of the substrate.

19. The method of claim 18 , further comprising:
forming a third dielectric layer over the second dielectric layer and/or the upper surface of the substrate; and
patterning the third dielectric layer to remove portions of the third dielectric layer from the upper surface of the substrate.

20. The method of claim 19 , wherein the first, second, and third dielectric layers comprise the same material as one another.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Chiao-Chun
• Chen Chih-Ming
• Yu Chung-Yi
• Pan Lung Yuan

Classifications

• B81B2203/0136

  Comb structures · CPC title

• B81B2201/033

  Comb drives · CPC title

• B81B3/0086

  Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage · CPC title

• B81C2201/0125

  Blanket removal, e.g. polishing · CPC title

• H02N2/22

  Methods relating to manufacturing, e.g. assembling, calibration · CPC title