Multi-level buck converter and associate control circuit thereof

Patent metadata

Field	Value
Publication number	US-12355357-B2
Application number	US-202318162287-A
Country	US
Kind code	B2
Filing date	Jan 31, 2023
Priority date	May 26, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A control circuit for controlling a multi-level buck converter having N pairs of switches serially connected between an input terminal and a logic ground, wherein N is an integer equal to or greater than 2. The control circuit has a comparing circuit, a selecting circuit and a delay circuit. The comparing circuit compares a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter with a reference signal to generate a comparing signal. The selecting circuit generates N set signals based on the comparing signal. The delay circuit delays the N set signals to provide N delay set signals to control the N pairs of switches when the output voltage signal falls in
( 1 ± k ⁢ % ) ⨯ 1 N
of an input voltage signal of the multi-level buck converter,

( 1 ± k ⁢ % ) ⨯ 2 N
of the input voltage signal, . . . , or

( 1 ± k ⁢ % ) ⨯ N - 1 N
of the input voltage signal, wherein k is a proportional coefficient.

First claim

What is claimed is:

1. A control circuit for controlling a multi-level buck converter having N pairs of switches serially connected between an input terminal and a logic ground, and wherein N is an integer equal to or greater than 2, the control circuit comprising:
a comparing circuit configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal;
a selecting circuit configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal; and
a delay circuit configured to delay the N set signals to provide N delay set signals to control the N pairs of switches when the output voltage signal falls in

(

1
±

k
⁢
%

)

×

1
N

 of an input voltage signal of the multi-level buck converter,

(

1
±

k
⁢
%

)

×

2
N

 of the input voltage signal, . . . , or

(

1
±

k
⁢
%

)

×

N
-
1

N

 of the input voltage signal, wherein k is a proportional coefficient.

2. The control circuit of claim 1 , wherein the delay circuit comprises:
a voltage divider configured to receive the input voltage signal to generate N−1 dividing voltage signals, wherein for each i=1, . . . , N−1, the i th dividing voltage signal of the N−1 dividing voltage signals is equal to

i
N

 of the input voltage signal;
N−1 hysteresis comparators configured to generate N−1 determining signals, wherein for each i=1, . . . , N−1, the i th hysteresis comparator is configured to receive the output voltage signal and the i th dividing voltage signal, and further configured to compare the output voltage signal with the i th dividing voltage signal to generate the i th determining signal of the N−1 determining signal;
an OR logic gate configured to receive the N−1 determining signals, and configured to conduct a logic OR operation of the N−1 determining signals to generate a delay enable signal; and
a plurality of delay modules, wherein each of the plurality of delay modules is configured to receive the delay enable signal and one corresponding set signal of the N set signals, and further configured to generate one corresponding delay set signal based on the delay enable signal and the corresponding set signal.

3. The control circuit of claim 2 , wherein when N is an odd number, the quantity of the delay modules is equal to (N−1)/2, and when N is an even number, the quantity of the delay modules is equal to N/2.

4. The control circuit of claim 1 , wherein when N is an odd number, for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i−1) th set signal of the N set signals to provide the (2i−1) th delay set signal of the N delay set signals.

5. The control circuit of claim 1 , wherein when N is an odd number, for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i+1) th set signal of the N set signals to provide the (2i+1) th delay set signal of the N delay set signals.

6. The control circuit of claim 1 , wherein when N is an odd number, for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i) th set signal of the N set signals to provide the (2i) th delay set signal of the N delay set signals.

7. The control circuit of claim 1 , wherein when N is an even number, for each i=1, . . . , N/2, the delay circuit is configured to delay the (2i−1) th set signal of the N set signals to provide the (2i−1) th delay set signal of the N delay set signals.

8. The control circuit of claim 1 , wherein when N is an even number, for each i=1, . . . , N/2, the delay circuit is configured to delay the (2i) th set signal of the N set signals to provide the (2i) th delay set signal of the N delay set signals.

9. The control circuit of claim 1 , wherein the proportional coefficient k is smaller than 10.

10. The control circuit of claim 1 , further comprising:
N COT controllers, wherein for each i=1, 2, . . . , N, the i th COT controller is configured to receive the i th delay set signal of the N delay set signals, the output voltage signal and the input voltage signal, and based on the i th delay set signal, the output voltage signal and the input voltage signal, the i th COT controller is further configured to generate an i th control signal to control the i th pair of switches of the N pairs of switches to perform a complementary on and off switching.

11. A multi-level buck converter, comprising:
N pairs of switches serially connected between an input terminal and a logic ground, wherein N is an integer equal to or greater than 2;
a comparing circuit configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal;
a selecting circuit configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal; and
a delay circuit configured to delay the N set signals to provide N delay set signals to control the N pairs of switches when the output voltage signal falls in

(

1
±

k
⁢
%

)

×

1
N

 of an input voltage signal of the multi-level buck converter,

(

1
±

k
⁢
%

)

×

2
N

 of

Assignees

• Monolithic Power Systems Inc

Inventors

• Han Di
• Jiang Jian

Classifications

• H02M3/157

  with digital control · CPC title

• H02M1/0003

  Details of control, feedback or regulation circuits · CPC title

• H02M7/4837

  Flying capacitor converters · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title