Multi-level switching power converter, and controller circuit and control method thereof

Patent metadata

Field	Value
Publication number	US-2020161967-A1
Application number	US-201916680599-A
Country	US
Kind code	A1
Filing date	Nov 12, 2019
Priority date	Nov 20, 2018
Publication date	May 21, 2020
Grant date	—

Abstract

A multi-level switching power converter includes a multi-level power stage circuit which converts an input power to an output power. The power stage circuit includes an inductor, a conversion capacitor and plural power switches. The controller circuit controls the multi-level power stage circuit and includes: a feedback pulse generator circuit which generates a trigger pulse; a first timer circuit and a second timer circuit which determine a first time period and a second time period respectively according to the trigger pulse; and an adjusting circuit which adjusts the first time period according to a difference between the voltage across the conversion capacitor and a reference voltage such that an average of the voltage across the conversion capacitor is substantially equal to a level of the reference voltage.

First claim

What is claimed is:

1 . A multi-level switching power converter, comprising:
a multi-level power stage circuit, configured to operably convert an input power to an output power by multi-level power conversion; and a controller circuit, configured to operably control the multi-level power stage circuit; wherein the multi-level power stage circuit includes:
an inductor, coupled between a switching node and a first node;
a conversion capacitor, configured to operably generate at least one proportion voltage level by capacitive voltage division; and
plural power switches, coupled to the inductor and the conversion capacitor, and configured to operably control the coupling arrangement of the inductor and the conversion capacitor, such that the switching node is switched among the at least one proportion voltage level, a second node, and a third node, so that the multi-level power conversion is achieved, wherein a voltage across the conversion capacitor determines the at least one proportion voltage level;
wherein the first node, the second node and the third node are configured as one of the followings:
(1) the first node is coupled to the output power, the second node is coupled to the input power, and the third node is coupled to ground level, whereby the multi-level power stage circuit operates as a buck power stage circuit;
(2) the first node is coupled to the input power, the second node is coupled to the output power, and the third node is coupled to the ground level, whereby the multi-level power stage circuit operates as a boost power stage circuit; or,
(3) the first node is coupled to the ground level, the second node is coupled to the input power, and the third node is coupled to the output power, whereby the multi-level power stage circuit operates as an inverting buck-boost power stage circuit;

wherein the controller circuit includes:
a feedback pulse generator circuit, configured to operably generate a trigger pulse according to an output related signal and a reference signal, wherein the output related signal relates to the output power;
a phase splitting circuit, configured to operably generate at least a first phase pulse and a second phase pulse according to the trigger pulse;
plural timer circuits, coupled to the phase splitting circuit, wherein a first one of the plural timer circuits is configured to operably determine a first time period and generate a first pulse modulation signal according to the first phase pulse and the first time period, and a second one of the plural timer circuits is configured to operably determine a second time period and generate a second pulse modulation signal according to the second phase pulse and the second time period; and
an adjusting circuit, configured to operate as one of the followings:
(1) the adjusting circuit generating a first adjusting signal according to a difference between the voltage across the conversion capacitor and a reference voltage to control the timer circuit to adjust the first time period such that an average of the voltage across the conversion capacitor is substantially equal to a level of the reference voltage; or
(2) the adjusting circuit generating the first adjusting signal according to a difference between a voltage on the switching node and a reference voltage, and a duty ratio related signal, to control the timer circuit to adjust the first time period such that the proportion voltage level is substantially equal to a level of the reference voltage, wherein the duty ratio related signal relates to a duty ratio of the plural power switches.

2 . The multi-level switching power converter of claim 1 , wherein the controller circuit further includes another adjusting circuit, configured to operate as one of the followings:
(1) the another adjusting circuit generating a second adjusting signal according to the difference between the voltage across the conversion capacitor and the reference voltage to control the second timer circuit to adjust the second time period such that the average of the voltage across the conversion capacitor is substantially equal to the level of the reference voltage; or (2) the another adjusting circuit generating the second adjusting signal according to the difference between the voltage on the switching node and the reference voltage, and the duty ratio related signal, to control the second timer circuit to adjust the second time period such that the proportion voltage level is substantially equal to the level of the reference voltage; wherein a direction of adjusting the second time period by the second adjusting signal is complementary to a direction of adjusting the first time period by the first adjusting signal.

3 . The multi-level switching power converter of claim 1 , wherein the timer circuit includes:
a current source, configured to operably provide a predetermined current; a timer capacitor circuit, configured to operably generate an integration signal according to a timer current, wherein the timer current relates to the predetermined current; a timer comparison circuit, configured to operably generate a timer comparison signal according to the integration signal and a threshold voltage; and a timer logic circuit, configured to operably generate a timer output signal according to a timer input signal and the integration signal, wherein the timer output signal has a predetermined time period, and a time length of the predetermined time period is determined by the timer circuit according to the timer current, a capacitance of the timer capacitor circuit, and a level of the threshold voltage; wherein the timer input signal of the timer circuit corresponds to the first phase pulse, and the timer output signal corresponds to the first pulse modulation signal, and the predetermined time period corresponds to the first time period.

4 . The multi-level switching power converter of claim 3 , wherein the timer circuit adjusts the first time period according to the first adjusting signal by at least one of the following ways:
(1) the first adjusting signal adjusting the timer current to adjust the first time period; (2) the first adjusting signal adjusting the threshold voltage to adjust the first time period; or (3) the first adjusting signal adjusting the capacitance of the timer capacitor circuit in an analog or digital manner to adjust the first time period.

5 . The multi-level switching power converter of claim 4 , wherein the adjusting circuit includes at least one of the followings:
(1) a transconductor circuit, configured to operate as one of the followings: (1a) generating an adjusting output signal according to the difference between the voltage across the conversion capacitor and the reference voltage; or (1b) generating the adjusting output signal according to the difference between the voltage on the switching node and the reference voltage, and the duty ratio related signal, wherein the adjusting output signal is in current form and provides a current branch shunted to the current source and the timer capacitor circuit to adjust the timer current; or (2) a voltage gain circuit, configured to operate as one of the followings: (2a) generating the adjusting output signal according to the difference between the voltage across the conversion capacitor and the reference voltage; or (2b) generating the adjusting output signal according to the difference between the voltage on the switching node and the reference voltage, and the duty ratio related signal, wherein the adjusting output signal is in voltage form and is configured to adjust the threshold voltage; wherein the adjusting output signal corresponds to the first adjusting signal.

6 . The multi-level switching power converter of claim 1 , wherein the first pulse modulation signal

Assignees

• Richtek Technology Corp

Inventors

• Chuang Yung-Chun
• Huang Tsung-Wei

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M1/143

  using compensating arrangements (for reducing noise from the supply in transmission systems H04B15/005) · CPC title

• H02M7/4837

  Flying capacitor converters · CPC title

• H02M7/4833

  Capacitor voltage balancing · CPC title

• H02M1/0095

  Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck · CPC title