Integrated circuit (IC) package substrate with embedded trace substrate (ETS) layer on a substrate, and related fabrication methods

Patent metadata

Field	Value
Publication number	US-12354935-B2
Application number	US-202117405494-A
Country	US
Kind code	B2
Filing date	Aug 18, 2021
Priority date	Aug 25, 2020
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (μm)/5.0 μm or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.

First claim

What is claimed is:

1. A package substrate for an integrated circuit (IC) package, comprising:
a substrate, comprising:
an upper substrate metallization layer comprising one or more substrate metal interconnects; and

an embedded trace substrate (ETS) interconnect layer adjacent to the upper substrate metallization layer of the substrate, the ETS interconnect layer comprising one or more ETS interconnects embedded in a dielectric material, wherein the one or more ETS interconnects each have an ETS interconnect outer surface that is flush with an outer surface of the dielectric material; each ETS interconnect among the one or more ETS interconnects coupled to a corresponding substrate metal interconnect among the one or more substrate metal interconnects in the upper substrate metallization layer of the substrate; and
one or more metal pillar interconnects, wherein each one or more metal pillar interconnects are coupled to an ETS interconnect among the one or more ETS interconnects, and to the corresponding substrate metal interconnect among the one or more substrate metal interconnects,
wherein:
the ETS interconnect layer comprises an ETS interconnect layer outer surface;
the one or more ETS interconnects are adjacent to the ETS interconnect layer outer surface; and
the one or more metal pillar interconnects each comprises a first surface extending a distance from the ETS interconnect layer outer surface.

2. The package substrate of claim 1 , wherein the substrate comprises a cored substrate.

3. The package substrate of claim 1 , wherein the substrate comprises a coreless substrate.

4. The package substrate of claim 1 , wherein a line-spacing ratio (L/S) of each ETS interconnect among the one or more ETS interconnects is less than 5.0/5.0.

5. The package substrate of claim 1 , wherein the distance of a portion of the one or more metal pillar interconnects extending from the ETS interconnect layer outer surface is equal to or greater than five ( 5 ) micrometers (um).

6. The package substrate of claim 1 , wherein each of the one or more metal pillar interconnects extends through the one or more ETS interconnects and is coupled to the corresponding substrate metal interconnect among the one or more substrate metal interconnects in the upper substrate metallization layer of the substrate.

7. The package substrate of claim 1 , wherein each of the one or more metal pillar interconnects comprises a second surface coupled to the corresponding substrate metal interconnect among the one or more substrate metal interconnects in the upper substrate metallization layer of the substrate.

8. The package substrate of claim 7 , wherein each of the one or more metal pillar interconnects has a thickness of a second distance equal to or greater than ten (10) micrometers (μm) between the first surface of each of the one or more metal pillar interconnects and the second surface of each of the one or more metal pillar interconnects.

9. The package substrate of claim 1 , wherein a ratio of a thickness of the one or more metal pillar interconnects to a thickness of the ETS interconnect layer is at least 1.4.

10. The package substrate of claim 1 , wherein a line-spacing ratio (L/S) of the one or more metal pillar interconnects is less than 5.0/5.0.

11. The package substrate of claim 1 , further comprising a solder resist layer comprising a second surface and a third surface coupled to the ETS interconnect layer, at least one of the one or more metal pillar interconnects further extending through the solder resist layer and further extending a second distance above the second surface of the solder resist layer.

12. The package substrate of claim 1 , wherein:
the substrate further comprises at least one additional substrate metallization layer adjacent to the upper substrate metallization layer, wherein the upper substrate metallization layer is disposed between the ETS interconnect layer and the at least one additional substrate metallization layer; and
each of the at least one additional substrate metallization layer comprises one or more additional substrate metal interconnects; and
at least one of the one or more additional substrate metal interconnects are coupled to at least one of the one or more substrate metal interconnects in the upper substrate metallization layer.

13. An integrated circuit (IC) package, comprising:
a package substrate, comprising:
a substrate, comprising:
an upper substrate metallization layer comprising one or more substrate metal interconnects; and

an embedded trace substrate (ETS) interconnect layer adjacent to the upper substrate metallization layer of the substrate, the ETS interconnect layer comprising one or more ETS interconnects embedded in a dielectric material, wherein the one or more ETS interconnects each have an ETS interconnect surface that is flush with an outer surface of the dielectric material; and
each ETS interconnect among the one or more ETS interconnects coupled to a corresponding substrate metal interconnect among the one or more substrate metal interconnects in the upper substrate metallization layer of the substrate; and

a die coupled to at least one ETS interconnect among the one or more ETS interconnects in the ETS interconnect layer; and
one or more metal pillar interconnects each coupling an ETS interconnect among the one or more ETS interconnects to the corresponding substrate metal interconnect among the one or more substrate metal interconnects,
wherein:
the ETS interconnect layer comprises an ETS interconnect layer outer surface;
the one or more ETS interconnects are adjacent to the ETS interconnect layer outer surface; and
the one or more metal pillar interconnects each comprises a first surface extending a distance from the ETS interconnect layer outer surface.

14. The IC package of claim 13 , wherein:
the one or more ETS interconnects comprise a plurality of ETS interconnects;
a plurality of die interconnects coupled to the die; and
each die interconnect among the plurality of die interconnects is coupled to an ETS interconnect among the plurality of ETS interconnects.

15. The IC package of claim 14 , wherein:
the upper substrate metallization layer further comprises one or more second substrate metal interconnects; and
the ETS interconnect layer comprises one or more second ETS interconnects;
each second ETS interconnect among the one or more second ETS interconnects coupled to a second substrate metal interconnect among the one or more second substrate metal interconnects in the upper substrate metallization layer of the substrate; and
further comprising:
a second die;
a plurality of second die interconnects coupled to the second die;
each second die interconnect among the plurality of second die interconnects coupled to a second ETS interconnect among the one or more second ETS interconnects; and
at least one ETS interconnect among the one or more ETS interconnects that is coupled to at least one die interconnect among the plurality of die interconnects, is coupled to at least one second ETS interconnect among the one or more second ETS interconnects that is coupled to at least one second die interconnect among the plurality of second die interconnects.

16. The IC package of claim 13 , wherein each of the one or more metal pillar interconnects comprises a second surface coupled to the corresponding substrate metal interconnect among the one or more substrate metal interconnects in the upper substrate metallization layer of the substrate.

17. The IC package of claim 13 , wherein the substrat

Assignees

• Qualcomm Inc

Inventors

• Kang Kuiwon
• Kim Chin-Kwan
• Park Joonsuk

Classifications

• H10W70/6565

  recessed into the surface of the package substrates, interposers, or redistribution layers · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/05 Primary

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title