Contamination detection method

Patent metadata

Field	Value
Publication number	US-12354922-B2
Application number	US-202217746655-A
Country	US
Kind code	B2
Filing date	May 17, 2022
Priority date	May 17, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A method of forming an integrated circuit on a substrate is described herein. The method includes forming a first doped region of a detection structure on the substrate, the first doped region comprises a first doped conductivity type. The method forming a capacitor of the detection structure, which includes forming a second doped region of a second conductivity type opposite the first doped conductivity type, the second doped region surrounded by the first doped region. The second doped well comprises a top surface area smaller than a top surface area of the first doped region. The method includes performing parametric testing on the capacitor over a plurality of breakdown voltages. The method includes determining the gate oxide integrity of the capacitor based on the parametric testing over the plurality of breakdown voltages.

First claim

What is claimed:

1. A method of forming an integrated circuit, the method comprising:
forming a first doped region of a detection structure on a substrate, the first doped region comprises a first doping conductivity type;
forming a first capacitor of the detection structure, comprising:
forming a second doped region of a second doping conductivity type opposite the first doping conductivity type, the second doped region laterally surrounded by the first doped region, wherein the second doped region comprises a top surface area smaller than a top surface area of the first doped region;
forming a dielectric layer on the second doped region; and
forming an electrode disposed on the dielectric layer;

performing parametric testing on the first capacitor over a plurality of breakdown voltages; and
determining gate oxide integrity of the first capacitor as a result of performing the parametric testing over the plurality of breakdown voltages.

2. The method of claim 1 , further comprising:
forming the integrated circuit as a result of determining the gate oxide integrity of the first capacitor.

3. The method of claim 1 , wherein a plurality of contaminants are attracted to the first capacitor of the detection structure.

4. The method of claim 1 , further comprising:
forming a deep trench isolation oxide around the first doped region of the detection structure.

5. The method of claim 1 , wherein at least one length of the first capacitor is 20 μm.

6. The method of claim 5 , further comprising:
forming a second detection structure disposed in the first doped region, comprising:
forming a third doped region of the first doping conductivity type; and
forming a second capacitor.

7. The method of claim 6 , wherein the third doped region is disposed in the first doped region, and the second capacitor is laterally surrounded by the third doped region.

8. The method of claim 1 , further comprising:
forming a second capacitor of the detection structure, comprising:
forming a third doped well of the second doping conductivity type.

9. The method of claim 8 , wherein the second capacitor is disposed adjacent to the first capacitor and separated by the first doped region from the second doped region, and wherein the second capacitor is laterally surrounded by the first doped region.

10. The method of claim 8 , wherein a sum of the top surface area of the first capacitor and a top surface area of the second capacitor is smaller than the top surface area of the first doped region.

11. The method of claim 1 , further comprising:
forming a deep trench isolation oxide disposed adjacent to the first doped region and laterally surrounding the first doped region.

12. The method of claim 1 , wherein an area of the first doped region is 100,000 μm 2 .

13. The method of claim 1 , wherein the detection structure is formed in and along a scribe line of the substrate.

14. The method of claim 1 , wherein the first doping conductivity type is p-type and the second doping conductivity type is n-type.

15. The method of claim 1 , further comprising:
forming a bottom doped region of the first doping conductivity type, the bottom doped region formed under the first capacitor and under the first doped region.

Assignees

• Texas Instruments Inc

Inventors

• Guo Honglin
• Higgins Robert M

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G01N27/92

  by investigating breakdown voltage (G01N27/60, G01N27/62 take precedence) · CPC title