Dynamic adjustment of offset voltages for reading memory cells in a memory device

Patent metadata

Field	Value
Publication number	US-12354670-B2
Application number	US-202218054879-A
Country	US
Kind code	B2
Filing date	Nov 11, 2022
Priority date	Sep 4, 2020
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A memory device to manage the assignment of offset voltages for read operations, and to adjust read voltages using the offset voltages. The offset voltages are dynamically adjusted by a controller during operation of the memory device in response to read errors. In one approach, a first bin of offset voltages is assigned to a first region of a storage media. The first offset voltages are used to adjust read voltages for reading a page of first memory cells in the first region. The controller determines that at least one error has occurred in reading the page. In response to determining the error, the controller determines second offset voltages that can be used to read the first memory cell without causing a read error. Based on the second offset voltages, the controller identifies third offset voltages for assigning to the first region. The third offset voltages are used for adjusting read voltages for subsequent reads of pages in the first region. The third offset voltages can be assigned from an existing offset voltage bin, or a new offset voltage bin can be generated for the assignment.

First claim

What is claimed is:

1. An apparatus comprising:
a storage media having memory cells; and
a controller configured to:
store offset voltages for adjusting read voltages, wherein magnitudes of the offset voltages are based on a number of program/erase cycles;
adjust, based on the offset voltages, read voltages for reading first memory cells;
read the first memory cells using the adjusted read voltages;
determine that an error occurred in reading the first memory cells; and
in response to determining that the error occurred, update the offset voltages.

2. The apparatus of claim 1 , wherein:
updating the offset voltages comprises determining first offset voltages for which the first memory cells are read without error; and
the updated offset voltages are based on the first offset voltages.

3. The apparatus of claim 1 , wherein the offset voltages are assigned to respective regions of the memory cells.

4. The apparatus of claim 3 , wherein the updated offset voltages are assigned to a region in which the first memory cells are located.

5. The apparatus of claim 1 , wherein the controller is further configured to determine a bit error rate when reading the first memory cells, and the offset voltages are updated based on the bit error rate.

Assignees

• Micron Technology Inc

Inventors

• Kaynak Mustafa N
• Parthasarathy Sivagnanam
• Khayat Patrick Robert

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title