Dynamic adjustment of offset voltages for reading memory cells in a memory device

Patent metadata

Field	Value
Publication number	US-11514989-B2
Application number	US-202017013423-A
Country	US
Kind code	B2
Filing date	Sep 4, 2020
Priority date	Sep 4, 2020
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A memory device to manage the assignment of offset voltages for read operations, and to adjust read voltages using the offset voltages. The offset voltages are dynamically adjusted by a controller during operation of the memory device in response to read errors. In one approach, a first bin of offset voltages is assigned to a first region of a storage media. The first offset voltages are used to adjust read voltages for reading a page of first memory cells in the first region. The controller determines that at least one error has occurred in reading the page. In response to determining the error, the controller determines second offset voltages that can be used to read the first memory cell without causing a read error. Based on the second offset voltages, the controller identifies third offset voltages for assigning to the first region. The third offset voltages are used for adjusting read voltages for subsequent reads of pages in the first region. The third offset voltages can be assigned from an existing offset voltage bin, or a new offset voltage bin can be generated for the assignment.

First claim

What is claimed is:

1. A system comprising:
a storage media comprising regions of memory cells; and
a controller configured to:
determine first offset voltages assigned to a first region of the storage media for adjusting read voltages when reading memory cells in the first region;
adjust, using the first offset voltages, read voltages for reading first memory cells in the first region;
read, using the adjusted read voltages, the first memory cells;
determine that an error has occurred in reading the first memory cells;
in response to determining that the error has occurred, determine second offset voltages for which the first memory cells are read without the error;
determine third offset voltages using offset voltages selected from the second offset voltages; and
assign the third offset voltages to the first region for adjusting read voltages to read memory cells in the first region.

2. The system of claim 1 , wherein:
the first region is a memory block of a flash memory device;
the first offset voltages are selected from a first bin;
the second offset voltages are selected from a second bin;
determining the third offset voltages comprises generating a new bin that includes the third offset voltages; and
assigning the third offset voltages comprises assigning the new bin to the first region.

3. The system of claim 1 , wherein the controller is further configured to:
receive, from a host device, a command to read data stored in the first region;
wherein the first offset voltages are determined in response to receiving the command.

4. The system of claim 1 , wherein:
the first offset voltages are stored in a first bin; and
the second offset voltages are stored in a second bin.

5. The system of claim 1 , wherein the controller is further configured to assign, in response to one or more read errors, offset voltages for adjusting read voltages when reading memory cells of the storage media.

6. The system of claim 1 , wherein a first bin of offset voltages includes the first offset voltages, a minimum of voltage differences between the offset voltages of the first bin is a first minimum, and the controller is further configured to:
determine a number of errors that have occurred in reading memory cells in the first region;
determine that the number of errors is greater than a predetermined threshold; and
in response to determining that the number of errors is greater than the predetermined threshold, generate a second bin of offset voltages, wherein a minimum of voltage differences between the offset voltages of the second set is a second minimum, and the second minimum is less than the first minimum;
wherein the third offset voltages are assigned from the second bin.

7. A method comprising:
receiving, from a host device by a controller, a command to read data stored in a region of a memory device;
in response to receiving the command, determining first offset voltages that are assigned to the region for adjusting read voltages when reading memory cells in the region;
adjusting, using the first offset voltages, read voltages;
reading first memory cells in the region using the adjusted read voltages;
determining that an error has occurred in reading the first memory cells;
in response to determining that the error has occurred, determining second offset voltages for which the first memory cells can be read;
determining third offset voltages using offset voltages selected from the second offset voltages; and
assigning the third offset voltages to the region for adjusting read voltages.

8. The method of claim 7 , wherein:
an existing bin includes the third offset voltages;
determining the third offset voltages comprises:
determining a voltage difference between one of the third offset voltages for a valley, and one of the second offset voltages for the valley; and
determining that the voltage difference is less than a predetermined value; and

assigning the third offset voltages comprises assigning the existing bin to the region.

9. The method of claim 7 , wherein determining the third offset voltages comprises:
determining a voltage difference between one of the second offset voltages for a valley, and an offset voltage for the valley in an existing bin of offset voltages;
determining that the voltage difference is greater than a predetermined value; and
in response to determining that the voltage difference is greater than the predetermined value, generating a new bin of offset voltages;
wherein the new bin is assigned to the region.

10. The method of claim 7 , wherein:
the controller assigns offset voltages to regions of the memory device using existing bins; and
determining the third offset voltages comprises generating a new bin of offset voltages, wherein the new bin is added to the existing bins for use by the controller in assigning offset voltages to regions of the memory device with an increased voltage resolution; and
assigning the third offset voltages comprises assigning the new bin to the region.

11. The method of claim 7 , wherein the first offset voltages are included in a first bin of offset voltages, the method further comprising:
generating a second bin of offset voltages;
wherein determining the third offset voltages comprises assigning the second bin to the region.

12. The method of claim 7 , wherein the controller assigns existing bins to regions of the memory device, the method further comprising:
determining a bit error rate when reading memory cells of the memory device; and
increasing a number of the existing bins based on the determined bit error rate.

13. The method of claim 7 , wherein:
magnitudes of the first offset voltages are based on a number of program/erase cycles; and
the first memory cells are configured to be programmed in a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode.

14. The method of claim 7 , further comprising:
prior to receiving the command, determining a storage charge loss for a valley corresponding to the first memory cells; and
determining magnitudes of offset voltages for the valley based on the storage charge loss.

15. The method of claim 7 , further comprising:
determining a maximum storage charge loss for a valley;
determining, based on the maximum storage charge loss, offset voltages for the valley used in existing bins managed by the controller; and
assigning, by the controller, regions of the memory device to one of the existing bins.

16. The method of claim 15 , further comprising:
determining a margin for reading memory cells of the memory device;
determining that the margin is greater than a predetermined threshold; and
in response to determining that the margin is greater than the predetermined threshold, disabling assignment of offset voltages to regions of the memory device until determining that a read error has occurred.

17. The method of claim 7 , further comprising:
determining an extent of storage charge loss for a valley used for reading memory cells of the memory device;
wherein determining the third offset voltages is further based on the extent of storage charge loss for the valley.

18. A non-transitory computer-readable medium storing instructions which, when executed on at least one processing device, cause the at least one processing device to:
determine first offset voltages of a first bin that is assigned to a block of a memory device;
adjust, using the first offset voltages, read voltages for reading memory cells in the block;
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Assignees

• Micron Technology Inc

Inventors

• Kaynak Mustafa N
• Parthasarathy Sivagnanam
• Khayat Patrick Robert

Classifications

• G11C29/021

  in voltage or current generators · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title