Spacer film scheme form polarization improvement

Patent metadata

Field	Value
Publication number	US-12354633-B2
Application number	US-202418763154-A
Country	US
Kind code	B2
Filing date	Jul 3, 2024
Priority date	Jul 29, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

First claim

What is claimed is:

1. An integrated chip, comprising:
a lower electrode;
a high-k material structure disposed over the lower electrode;
an upper electrode disposed over a central region of the high-k material structure; and
a stressed dielectric spacer arranged on a peripheral region of the high-k material structure, wherein the high-k material structure has an orthorhombic phase concentration that varies between the central region and the peripheral region.

2. The integrated chip of claim 1 , wherein the stressed dielectric spacer physically contacts the high-k material structure along an interface that extends both vertically and horizontally.

3. The integrated chip of claim 1 , wherein the orthorhombic phase concentration increases from the central region of the high-k material structure to the peripheral region of the high-k material structure.

4. The integrated chip of claim 1 , wherein the stressed dielectric spacer has a stress with a magnitude of between approximately 100 MPa (megapascals) and approximately 1000 MPa.

5. The integrated chip of claim 1 , wherein the orthorhombic phase concentration within the peripheral region has a maximum orthorhombic phase concentration of greater than approximately 70%.

6. The integrated chip of claim 1 , wherein at least a part of the central region of the high-k material structure is recessed below the peripheral region of the high-k material structure.

7. A device, comprising:
a bottom electrode;
a ferroelectric layer disposed on the bottom electrode;
a top electrode disposed on the ferroelectric layer; and
a spacer layer disposed on the ferroelectric layer and adjacent to the top electrode, wherein the ferroelectric layer has a higher concentration of orthorhombic phase within an edge region than within a central region.

8. The device of claim 7 , wherein the ferroelectric layer further comprises non-zero concentrations of a tetragonal phase and a monoclinic phase, the non-zero concentrations of the tetragonal phase and the monoclinic phase being lower than a concentration of the orthorhombic phase within the ferroelectric layer.

9. The device of claim 7 , wherein a maximum orthorhombic phase concentration within the edge region is more than 30% larger than a maximum orthorhombic phase concentration within the central region.

10. The device of claim 7 , wherein a concentration of the orthorhombic phase within the central region is greater than approximately 40%.

11. The device of claim 7 , wherein the spacer layer is configured to induce an increase of the orthorhombic phase within parts of the ferroelectric layer.

12. The device of claim 7 , wherein the spacer layer comprises nitrogen.

13. The device of claim 7 , wherein the ferroelectric layer has interior sidewalls forming a recess, the top electrode being arranged laterally and directly between the interior sidewalls of the ferroelectric layer.

14. The device of claim 7 , wherein the spacer layer comprises a silicon nitride material having a refractive index of less than approximately 1.9 as measured at 633 nm.

15. A method of forming an integrated chip (IC), comprising:
forming a lower electrode layer;
forming a ferroelectric layer over the lower electrode layer;
forming an upper electrode over the ferroelectric layer;
forming a spacer onto the ferroelectric layer and adjacent to the upper electrode;
patterning the ferroelectric layer and the lower electrode layer outside of the upper electrode and the spacer to form a ferroelectric data storage structure and a lower electrode; and
wherein the ferroelectric data storage structure has a higher concentration of orthorhombic phase within a peripheral region that is directly below the spacer than within a central region.

16. The method of claim 15 , further comprising:
forming a lower insulating structure over a substrate;
forming the lower electrode layer between sidewalls of the lower insulating structure;
performing a planarization process to remove a part of the lower electrode layer from over the lower insulating structure; and
forming the ferroelectric layer onto the lower electrode layer after performing the planarization process.

17. The method of claim 16 , wherein the spacer comprises a silicon nitride material formed by a vapor deposition technique that uses reacting gases including a silane gas and an ammonia gas.

18. The method of claim 17 , wherein the silane gas is introduced into a process chamber at a flow rate of between approximately 10 sccm (standard cubic centimeters per minute) and approximately 100 sccm.

19. The method of claim 17 , wherein a ratio of the ammonia gas to the silane gas is between approximately 0.8 and approximately 3.

20. The method of claim 17 , wherein the vapor deposition technique is performed at a power that is in a range of between approximately 10 Watts (W) and approximately 250 W, at a pressure of between approximately 3 torr and approximately 6 torr, and at a temperature of between approximately 200° Celsius (C) and approximately 400° C.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manfacturing Company Ltd

Inventors

• Lin Tzu-Yu
• Chang Yao-Wen

Classifications

• H10B51/30

  characterised by the memory core region · CPC title

• H10D64/671

  the conductor having lateral variation in doping or structure · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• H10B53/20

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title