Method for an internal command from a plurality of processing cores with memory sub-system that cache identifiers for access commands

Patent metadata

Field	Value
Publication number	US-12353928-B2
Application number	US-202418643656-A
Country	US
Kind code	B2
Filing date	Apr 23, 2024
Priority date	Apr 7, 2020
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.

First claim

What is claimed is:

1. An apparatus, comprising:
processing circuitry associated with one or more memory devices and configured to cause the apparatus to:
receive an access command to perform an access operation on a transfer unit of a memory sub-system, wherein the transfer unit is associated with one or more logical blocks;
store an identifier associated with an internal command in a shared memory that is accessible by a plurality of cores of the memory sub-system based at least in part on receiving the access command;
determine whether the access operation was completed based at least in part on storing the identifier; and
update the internal command based at least in part on determining that the access operation was not completed.

2. The apparatus of claim 1 , wherein determining whether the access command was completed comprises the processing circuitry configured to cause the apparatus to:
compare the identifier to one or more second identifiers stored in the shared memory.

3. The apparatus of claim 1 , wherein the processing circuitry is further configured to cause the apparatus to:
issue, based at least in part on updating the internal command, the updated internal command to perform the access operation on the memory sub-system based at least in part on the internal command being associated with the access command that was not completed.

4. The apparatus of claim 1 , wherein the internal command is updated by a first core of the plurality of cores.

5. The apparatus of claim 4 , wherein the processing circuitry is further configured to cause the apparatus to:
issue, to one or more second cores of the plurality of cores, one or more second internal commands to perform one or more second access operations on the memory sub-system, wherein at least a portion of the one or more second access operations are performed concurrently with updating the internal command.

6. The apparatus of claim 4 , wherein the processing circuitry is further configured to cause the apparatus to:
transmit, by the first core of the plurality of cores, an indication that the access command was successfully performed based at least in part on updating the internal command.

7. The apparatus of claim 6 , wherein the processing circuitry is further configured to cause the apparatus to:
refraining, based at least in part on transmitting the indication, from updating the internal command based at least in part on determining that the access operation was completed.

8. The apparatus of claim 1 , wherein the processing circuitry is further configured to cause the apparatus to:
perform the access operation based on receiving the access command, wherein storing the identifier associated with the internal command is based at least in part on performing the access operation, and wherein the identifier comprises an indication of a status of the access operation.

9. A method by a memory sub-system, comprising:
receiving an access command to perform an access operation on a transfer unit of the memory sub-system, wherein the transfer unit is associated with one or more logical blocks;
storing an identifier associated with an internal command in a shared memory that is accessible by a plurality of cores of the memory sub-system based at least in part on receiving the access command;
determining whether the access operation was completed based at least in part on storing the identifier; and
updating the internal command based at least in part on determining that the access operation was not completed.

10. The method of claim 9 , wherein determining whether the access command was completed comprises:
comparing the identifier to one or more second identifiers stored in the shared memory.

11. The method of claim 9 , further comprising:
issuing, based at least in part on updating the internal command, the updated internal command to perform the access operation on the memory sub-system based at least in part on the internal command being associated with the access command that was not completed.

12. The method of claim 9 , wherein the internal command is updated by a first core of the plurality of cores.

13. The method of claim 12 , further comprising:
issuing, to one or more second cores of the plurality of cores, one or more second internal commands to perform one or more second access operations on the memory sub-system, wherein at least a portion of the one or more second access operations are performed concurrently with updating the internal command.

14. The method of claim 12 , further comprising:
transmitting, by the first core of the plurality of cores, an indication that the access command was successfully performed based at least in part on updating the internal command.

15. The method of claim 14 , further comprising:
refraining, based at least in part on transmitting the indication, from updating the internal command based at least in part on determining that the access operation was completed.

16. The method of claim 9 , further comprising:
performing the access operation based on receiving the access command, wherein storing the identifier associated with the internal command is based at least in part on performing the access operation, and wherein the identifier comprises an indication of a status of the access operation.

17. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
receive an access command to perform an access operation on a transfer unit of a memory sub-system, wherein the transfer unit is associated with one or more logical blocks;
store an identifier associated with an internal command in a shared memory that is accessible by a plurality of cores of the memory sub-system based at least in part on receiving the access command;
determine whether the access operation was completed based at least in part on storing the identifier; and
update the internal command based at least in part on determining that the access operation was not completed.

18. The non-transitory computer-readable medium of claim 17 , wherein the instructions to determine whether the access command was completed are executable by the one or more processors to:
compare the identifier to one or more second identifiers stored in the shared memory.

19. The non-transitory computer-readable medium of claim 17 , wherein the instructions are further executable by the one or more processors to:
issue, based at least in part on updating the internal command, the updated internal command to perform the access operation on the memory sub-system based at least in part on the internal command being associated with the access command that was not completed.

20. The non-transitory computer-readable medium of claim 17 , wherein the internal command is updated by a first core of the plurality of cores.

Assignees

• Micron Technology Inc

Inventors

• Traver John
• Shoen Jay R

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F12/0871 Primary

  Allocation or management of cache space · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F9/546

  Message passing systems or structures, e.g. queues · CPC title