Memory device for performing internal process and operating method thereof

Patent metadata

Field	Value
Publication number	US-10083722-B2
Application number	US-201715607699-A
Country	US
Kind code	B2
Filing date	May 30, 2017
Priority date	Jun 8, 2016
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

First claim

What is claimed is:

1. A memory device, comprising:
a buffer die having an internal command generator configured to receive from an external memory controller a first external command for performing at least one internal data processing operation by the memory device, and in response thereto to generate at least two internal commands for causing the memory device to execute corresponding internal memory operations to perform the at least one internal data processing operation;
a first core die and a second core die stacked together with the buffer die, each of the first and second core dies having a plurality of dynamic random access memory (DRAM) cells, the DRAM cells being arranged into at least a first memory cell group of the first core die and a second memory cell group of the second core die;
a plurality of through silicon vias (TSVs) extending through the first and second core dies so as to connect to the buffer die;
at least two independent channels each associated with a corresponding one of the first and second memory cell groups, the at least two independent channels each including a corresponding set of the TSVs; and
a common internal processing channel shared among the first and second memory cell groups of the first and second core dies.

2. The memory device of claim 1 , wherein each of the at least two independent channels include a corresponding independent data bus for the corresponding memory cell group, and wherein the common internal processing channel includes a common internal data bus which is shared among the at least two memory cell groups.

3. The memory device of claim 1 , wherein each of the at least two independent channels include a corresponding independent command/address bus for the associated memory cell group, and wherein the common internal processing channel includes a common internal command/address bus which is shared among the at least two memory cell groups.

4. The memory device of claim 1 , wherein each of the at least two independent channels include a corresponding independent command/address bus for the associated memory cell group, and the memory device further comprising at least two independent internal command/address signal buses each associated with one of the at least two memory cell groups.

5. The memory device of claim 1 , wherein the common internal processing channel includes at least some of the TSVs, the TSVs of the common internal processing channel being shared by at least two of the memory cell groups when the memory device performs the at least one internal data processing operation.

6. The memory device of claim 1 , wherein the first core die includes at least a first data processor associated with the first memory cell group, wherein the second core die includes at least a second data processor associated with the second memory cell group, wherein the data processors are configured to perform the at least one internal data processing operation in response to at least one control signal provided by the internal command generator.

7. The memory device of claim 6 , wherein the at least one internal data processing operation comprises at least one of a data addition operation, an exclusive OR operation, a data subtraction operation, and a data multiplication operation.

8. The memory device of claim 1 , wherein when the external memory device receives a second external command from the memory controller which is a normal command, then the normal command is provided to one of the memory cell groups through its associated independent channel.

9. A memory device, comprising:
a buffer die having an internal command generator configured to receive from an external memory controller a first external command for performing at least one internal data processing operation by the memory device, and in response thereto to generate at least two internal commands for causing the memory device to execute corresponding internal memory operations to perform the at least one internal data processing operation;
at least one core die stacked together with the buffer die, the at least one core die having a plurality of dynamic random access memory (DRAM) cells arranged into a plurality of memory cell groups;
a plurality of through silicon vias (TSVs) extending through the at least one core die so as to connect to the buffer die; and
at least two independent channels each associated with a corresponding one of the memory cell groups, the at least two independent channels each comprising a corresponding set of the TSVs,
wherein at least some of the TSVs are shared by at least two of the plurality of memory cell groups when the memory device performs the at least one internal data processing operation.

10. The memory device of claim 9 , wherein the at least some of the TSVs which are shared by at least two of the plurality of the memory cell groups comprise a common internal processing channel shared among the plurality of memory cell groups.

11. The memory device of claim 9 , wherein the first external command comprises at least one of a data copy command, a data swap command, a read-modify-write command, and a mask-write command.

12. The memory device of claim 9 , further comprising a plurality of data processors, each data processor being associated with one of the memory cell groups and provided on a same core die as the associated memory cell group, wherein the data processors are configured to perform the at least one internal data processing operation in response to at least one control signal provided by the internal command generator.

13. The memory device of claim 9 , wherein the at least one internal data processing operation comprises at least one of a data addition operation, an exclusive OR operation, a data subtraction operation, and a data multiplication operation.

14. The memory device of claim 9 , wherein when the memory device receives a second external command from the external memory controller which is a normal command, then the normal command is provided to one of the plurality of memory cell groups through its associated independent channel.

15. A memory device, comprising:
a plurality of dynamic random access memory (DRAM) cells arranged into a plurality of memory cell groups;
a plurality of independent channels each associated with a corresponding one of the plurality of memory cell groups;
an internal command generator configured to receive from an external memory controller at least a first external command for performing at least one internal data processing operation by the memory device, and in response thereto to generate at least two internal commands for causing corresponding memory operations to be executed to perform the at least one internal data processing operation; and
a common internal processing channel shared among the plurality of memory cell groups,
wherein the first external command comprises at least one of a data copy command, a data swap command, a read-modify-write command, and a mask-write command.

16. The memory device of claim 15 , wherein the plurality of independent channels each associated with a corresponding one of the at least two memory cell groups are configured for performing normal operations for the DRAM cells of the plurality of memory cell groups, and the common internal processing channel is shared among the at least two memory cell groups for performing internal data processing operations for the DRAM cells of the at least two memory cell groups.

17. The memory device of claim 15 , further comprising a plurality of data processors associated with one of the memory cell grou

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Reum
• Ryu Je-Min
• Kasibhatla Pavan Kumar

Classifications

• H10W90/00

  Package configurations · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C2207/2245

  Memory devices with an internal cache buffer · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title