Semiconductor device capable of performing in-memory processing

Patent metadata

Field	Value
Publication number	US-12353847-B2
Application number	US-202117401201-A
Country	US
Kind code	B2
Filing date	Aug 12, 2021
Priority date	Nov 16, 2020
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A semiconductor device includes a memory cell array, an address input circuit, a command input circuit, a data Input/Output (IO) circuit, a processing control circuit, a processing circuit, and a switch circuit. The processing control circuit includes a register array storing an address of an operand and determines whether an address provided from the address input circuit corresponds to the address stored in the register array. The processing circuit is configured to provide a processing result by performing an operation on data provided from the memory cell array. The switch circuit is configured to control a data path among the processing circuit, the data IO circuit, and the memory cell array and controls the data path to connect the memory cell array to the processing circuit when the address provided from the address input circuit corresponds to the address stored in the register array.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory cell array;
an address input circuit;
a command decoder configured to decode a signal provided from a command input circuit;
a data Input/Output (IO) circuit;
a processing control circuit including a register array storing a first address of an operand;
a processing circuit configured to provide a processing result by performing an operation on data provided from the memory cell array; and
a switch circuit configured to control a data path among the processing circuit, the data IO circuit, and the memory cell array,
wherein the processing control circuit determines whether a second address provided from the address input circuit corresponds to the first address stored in the register array, and
wherein the switch circuit controls the data path to connect the memory cell array to the processing circuit when the second address provided from the address input circuit corresponds to the first address stored in the register array.

2. The semiconductor device of claim 1 , wherein the processing control circuit further includes a register control circuit to store the first address in the register array.

3. The semiconductor device of claim 2 , wherein the register control circuit stores data provided to the data IO circuit according to an output of the command decoder as the first address in the register array when the second address provided from the address input circuit corresponds to a predetermined register address associated with the register array.

4. The semiconductor device of claim 3 , further comprising a mode register configured to store the predetermined register address.

5. The semiconductor device of claim 1 , wherein the processing control circuit further includes a command identification circuit configured to identify a command for an in-memory processing by comparing the first address in the register array and the second address provided from the address input circuit.

6. The semiconductor device of claim 5 , wherein the command identification circuit incudes:
an address comparing circuit configured to compare the first address in the register array with the second address provided from the address input circuit; and
a control signal generating circuit configured to output a match signal by combining an output from the address comparing circuit and an output from the command decoder.

7. The semiconductor device of claim 6 , wherein the address comparing circuit includes:
a row address comparator configured to compare the first address in the register array with a row address in the second address provided from the address input circuit; and
a column address comparator configured to compare the first address in the register array with a column address in the second address provided from the address input circuit.

8. The semiconductor device of claim 7 , wherein the command identification circuit further includes a table management circuit to manage a matching table to store a comparison result of the row address comparator.

9. The semiconductor device of claim 8 , wherein the table management circuit manages data stored in the matching table with reference to a command from the command decoder, and
wherein the comparison result of the row address comparator is stored in the matching table when a command from the command decoder is an active command, and the comparison result of the row address comparator is inactivated and stored in the matching table when a command from the command decoder is a precharge command.

10. The semiconductor device of claim 8 , wherein the register array further stores a flag indicating whether the first address is valid,
wherein the comparison result of the row address comparator is stored in the matching table when the flag is enabled, and the comparison result of the row address comparator is inactivated and stored in the matching table when the flag is disabled.

11. The semiconductor device of claim 8 ,
wherein the memory cell array comprises a plurality of banks, and
wherein the table management circuit stores the comparison result of the row address comparator in the matching table for each bank.

12. The semiconductor device of claim 11 , wherein the command identification circuit further includes a bank selection circuit to provide a comparison result selected from the matching table corresponding to a bank address of the second address provided from the address input circuit.

13. The semiconductor device of claim 12 , wherein the control signal generating circuit includes:
a first gate circuit configured to logically combine an output from the bank selection circuit and an indication that a read command or a write command has been provided from the command decoder; and
a second gate circuit configured to logically combine an output of the first gate circuit and a comparison result of the column address comparator.

14. The semiconductor device of claim 1 , wherein the register array further stores a setting signal to set the processing circuit, and the processing circuit changes a type of processing operation according to the setting signal.

15. The semiconductor device of claim 14 , wherein the processing circuit performs one selected according to the setting signal of a multiplication and accumulation operation, an addition operation, a subtraction operation, and a multiplication operation.

Assignees

• Sk Hynix Inc
• Univ Korea Res & Bus Found

Inventors

• Kim Seonwook
• Lee Wonjun
• Kim Changhyun

Classifications

• G06F15/7821

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06F7/523

  Multiplying only · CPC title

• G11C8/18

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title