Method for on-silicon integration of a component III-V and on-silicon integrated component III-V

Patent metadata

Field	Value
Publication number	US-12353068-B2
Application number	US-202218053959-A
Country	US
Kind code	B2
Filing date	Nov 9, 2022
Priority date	Nov 9, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A method for on-silicon integration of a III-V-based material component includes providing a first substrate having a silicon-based optical layer including a waveguide, transferring a second substrate of III-V-based material on the optical layer, and forming the III-V component from the second substrate, so as to enable a coupling between the waveguide and the III-V component, by preserving a III-V-based material layer extending laterally. The method also includes forming by epitaxy from the III-V layer, an InP:Fe-based structure laterally bordering the III-V component, forming a layer including contacts configured to contact the III-V component, and transferring a third silicon-based substrate onto the layer including the contacts.

First claim

The invention claimed is:

1. A method for on-silicon integration of a III-V-based material component comprising:
providing a first substrate comprising a silicon-based optical layer, said optical layer comprising at least one waveguide,
transferring a second III-V-based material substrate on the optical layer,
forming the component from the second substrate, in a proximity of the waveguide so as to enable a coupling between the waveguide and the component, by preserving a III-V-based material layer extending laterally from the component,
forming by epitaxy from the III-V-based material layer an InP:Fe-based structure laterally bordering the component,
forming a layer comprising contacts configured to electrically contact the component, on a face of the component opposite the optical layer, and
transferring a third silicon-based substrate on the layer comprising the contacts.

2. The integration method according to claim 1 , further comprising, after transfer of the third silicon-based substrate:
removing the first substrate and preserving the optical layer, and
forming at least one interconnection level on the optical layer, the at least one interconnection level comprising interconnections electrically connecting the contacts.

3. The integration method according to claim 2 , wherein removing the first substrate is performed so as to expose the optical layer, the method further comprising, after removing the first substrate, doping of a silicon-based zone of the optical layer.

4. The integration method according to claim 3 , further comprising, before the doping, at least one step carried out at a temperature greater than or equal to 600° C.

5. The integration method according to claim 3 , wherein doping the silicon-based zone comprises implantation of doping species.

6. The integration method according to claim 2 , wherein the first substrate is a substrate of the on-insulator semi-conductive type comprising a buried oxide layer between a first silicon bulk part and a second semi-conductor-based thin part, and wherein removing the first substrate comprises removing the first bulk part and the buried oxide layer.

7. The integration method according to claim 1 , wherein forming the component comprises:
thinning the second III-V-based material substrate so as to preserve a III-V-based material germination layer, and
formation of forming the component by localised epitaxy only on one part of the germination layer.

8. The integration method according to claim 7 , wherein the second III-V-based material substrate comprises a sacrificial layer inserted between a bulk part of the second substrate and a part configured to form the germination layer, and wherein the thinning comprises:
at least one from among a mechanical cropping of the bulk part of the second substrate and a selective chemical etching of the bulk part of the second substrate vis-à-vis the sacrificial layer, and
selective etching of the sacrificial layer vis-à-vis the layer configured to form the germination layer.

9. The integration method according to claim 1 , wherein forming the component comprises:
thinning the second III-V-based material substrate so as to preserve a III-V-based material germination layer,
forming by epitaxy of a stack of III-V-based material functional layers, on the germination layer, and
etching a part of the stack so as to form the component and the III-V-based material layer extending laterally from the component.

10. The integration method according to claim 1 , wherein forming the component comprises forming AlInGaAs or GaInAsP alloy-based quantum wells.

11. The integration method according to claim 1 , further comprising, before transferring the third substrate, forming a thermal conduction layer on at least one from among the layer comprising the contacts and the third substrate, so as to insert said thermal conduction layer between the third substrate and the layer comprising the contacts.

12. The integration method according to claim 1 , wherein the III-V-based material layer extending laterally from the component is N-doped InP-based.

Assignees

• Commissariat Energie Atomique
• Thales Sa

Inventors

• Neel Delphine
• Bitauld David

Classifications

• H10F71/139

  using temporary substrates · CPC title

• H10F71/128

  Annealing · CPC title

• H10F71/127

  The active layers comprising only Group III-V materials, e.g. GaAs or InP · CPC title

• G02F2203/50

  Phase-only modulation · CPC title

• G02F2202/108

  quantum wells · CPC title