Optoelectronic device and method of manufacture thereof

US2022013988A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2022013988-A1
Application numberUS-202117364837-A
CountryUS
Kind codeA1
Filing dateJun 30, 2021
Priority dateJul 6, 2020
Publication dateJan 13, 2022
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of fabricating an optoelectronic component, performed on a multi-layered wafer disposed on a substrate. The method comprises the steps of: etching the multi-layered wafer, thereby defining a slab and a multi-layered ridge, the slab having an upper surface below the ridge and being located between the multi-layered ridge and the substrate; selectively epitaxially growing a III-V semiconductor cladding adjacent to a first and second sidewall of the ridge, the cladding layer extending from the upper surface of the slab along the first and second sidewalls, and thereby cladding an optically active waveguide within the multi-layered ridge; and providing a first and second electrical contact, which electrically connect to a layer of the multi-layered ridge and the slab respectively.

First claim

Opening claim text (preview).

1 . A method of fabricating an optoelectronic component, performed on a multi-layered wafer disposed on a substrate, the method comprising the steps of: performing one or more etches to the multi-layered wafer, thereby defining a slab and a multi-layered ridge, the slab having an upper surface below the ridge and being located between the multi-layered ridge and the substrate; selectively epitaxially growing a III-V semiconductor cladding adjacent to a first and second sidewall of the ridge, the cladding layer extending from the upper surface of the slab along the first and second sidewalls, and thereby cladding an optically active waveguide within the multi-layered ridge; and providing a first and second electrical contact, which electrically connect to a layer of the multi-layered ridge and the slab respectively. 2 . The method of claim 1 , wherein the III-V semiconductor cladding is undoped. 3 . The method of claim 1 , wherein the III-V semiconductor cladding is doped with iron. 4 . The method of claim 1 , wherein the III-V semiconductor cladding is formed from one of: InP, GaAs, GaSb, or GaP. 5 . The method of claim 1 , wherein the multi-layered wafer includes one or more III-V semiconductor layers. 6 . The method of claim 1 , wherein the optically active waveguide forms a part of one of: a photodiode; an electro-absorption modulator; and a laser. 7 . The method of claim 1 , wherein the cladding extends from the upper surface of the slab along the first and second sidewalls of the ridge to a point equal in height to an upper surface of a doped layer of the multi-layered ridge. 8 . The method of claim 1 , wherein prior to a first etch of the multi-layered wafer, the method includes depositing a first mask over a region of the multi-layered wafer which is to form the multi-layered ridge, and subsequently etching the unmasked region. 9 . The method of claim 8 , wherein the first mask is retained after the etching, and is present during the selective epitaxial growth of the III-V semiconductor cladding layer. 10 . The method of claim 8 , wherein the first mask is formed of silicon dioxide. 11 . The method of claim 8 , wherein the first etch extends only part way into a base layer of the multi-layered wafer which is adjacent to the substrate. 12 .- 16 . (canceled) 17 . An optoelectronic device, comprising: a multi-layered ridge, containing an optically active waveguide; a slab, located between the multi-layered ridge and a substrate; a III-V semiconductor cladding, located adjacent to a first and second sidewall of the ridge, and extending from the upper surface of the slab along the first and second sidewalls, thereby cladding the optically active waveguide within the multi-layered ridge; and a first and second electrical contact, which electrically connect to a layer of the multi-layered ridge and the slab respectively. 18 . The optoelectronic device of claim 17 , wherein the III-V semiconductor cladding is undoped. 19 . The optoelectronic device of claim 17 , wherein the III-V semiconductor cladding is doped with iron. 20 . The optoelectronic device of claim 17 , wherein the III-V semiconductor cladding is formed from one of: InP and GaAs. 21 . The optoelectronic device of claim 17 , wherein the multi-layered ridge includes one or more III-V semiconductor layers. 22 . The optoelectronic device of claim 17 , wherein the optically active waveguide forms a part of one of: a photodiode; an electro-absorption modulator; and a laser. 23 . The optoelectronic device of claim 17 , wherein the cladding extends from the upper surface of the slab along the first and second sidewalls of the ridge to a point equal in height to an upper surface of a doped layer of the multi-layered ridge. 24 . The optoelectronic device of claim 17 , wherein the first electrical contact includes a metal layer, located on top of the multi-layered ridge, said metal layer being electrically connected to an uppermost layer of the multi-layered ridge, and also electrically connected to a first contact pad located on an upper surface of the cladding. 25 . The optoelectronic device of any of claim 17 , wherein the second electrical contact is provided in a via through the cladding, said second electrical contact being electrically connected to the slab and a second contact pad located on an upper surface of the cladding.

Assignees

Inventors

Classifications

  • Shapes of bodies · CPC title

  • comprising only Group III-V materials, e.g. GaAs · CPC title

  • The active layers comprising only Group III-V materials, e.g. GaAs or InP · CPC title

  • ridge; rib; strip loaded · CPC title

  • Ridge, rib or the like · CPC title

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What does patent US2022013988A1 cover?
A method of fabricating an optoelectronic component, performed on a multi-layered wafer disposed on a substrate. The method comprises the steps of: etching the multi-layered wafer, thereby defining a slab and a multi-layered ridge, the slab having an upper surface below the ridge and being located between the multi-layered ridge and the substrate; selectively epitaxially growing a III-V semicon…
Who is the assignee on this patent?
Rockley Photonics Ltd
What technology area does this patent fall under?
Primary CPC classification G02B6/12. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jan 13 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).