Memory devices and methods of making the same

Patent metadata

Field	Value
Publication number	US-12349608-B2
Application number	US-202117411032-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	Aug 24, 2021
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having a spacer element on a side of the electrode. The present disclosure provides a memory device including a first electrode having a side, the side has upper and lower portions, a spacer element on the lower portion of the side of the first electrode, a resistive layer on the upper portion of the side of the first electrode, and a second electrode laterally adjacent to the side of the first electrode. The second electrode has a top surface, in which the top surface has a concave profile.

First claim

What is claimed is:

1. A memory device comprising:
a first electrode having a side, the side has upper and lower portions;
a spacer element directly on the lower portion of the side of the first electrode;
a resistive layer directly on the upper portion of the side of the first electrode; and
a second electrode laterally adjacent to the side of the first electrode, the second electrode having a top surface, a bottom surface, and a first side, wherein the top surface of the second electrode has a concave profile, and wherein the bottom surface and the first side of the second electrode is directly on the resistive layer.

2. The device of claim 1 , wherein the first side of the second electrode forms an acute angle with the concave top surface of the second electrode.

3. The device of claim 2 , wherein the first side of the second electrode meets the top surface of the second electrode to provide a top edge of the second electrode.

4. The device of claim 3 , wherein the resistive layer and the spacer element are between the first electrode and the second electrode.

5. The device of claim 4 , wherein the resistive layer covers the spacer element.

6. The device of claim 5 , wherein the spacer element isolates the lower portion of the side of the first electrode from the resistive layer.

7. The device of claim 6 , wherein the resistive layer is laterally between the spacer element and the first side of the second electrode.

8. The device of claim 1 , wherein the resistive layer is below the bottom surface of the second electrode.

9. The device of claim 8 , wherein the second electrode has a second side, and the resistive layer extends to lie on the second side of the second electrode.

10. The device of claim 1 , wherein the first electrode has a top surface, the top surface of the first electrode has a substantially planar profile.

11. The device of claim 10 , wherein the top surface of the first electrode is uncovered by the resistive layer.

12. The device of claim 1 , further comprising a third electrode laterally adjacent to the first electrode, wherein the first electrode is laterally between the third electrode and the second electrode.

13. The device of claim 12 , wherein the third electrode has a top surface, and the top surface has a concave profile.

14. The device of claim 12 , wherein the resistive layer and the spacer element lie between the first electrode and the third electrode.

15. The device of claim 12 , wherein the third electrode has a bottom surface, and the resistive layer is below the bottom surface of the third electrode.

16. A method of forming a memory device comprising:
forming a first electrode having a side with upper and lower portions, the first electrode being formed above an inter-metal dielectric region;
forming a spacer element directly on the lower portion of the side of the first electrode;
forming a resistive layer directly on the upper portion of the side of the first electrode; and
forming a second electrode laterally adjacent to the side of the first electrode, the second electrode having a top surface, a bottom surface, and a first side, wherein the top surface of the second electrode has a concave profile, and wherein the bottom surface and the first side of the second electrode being formed directly on the resistive layer.

17. The method of claim 16 , wherein the forming of the spacer element includes depositing of a spacer element layer on the side of the first electrode, and etching the spacer element layer to expose the upper portion of the side of the first electrode.

18. The method of claim 16 , wherein the forming of the resistive layer includes conformal deposition of the resistive layer on the upper portion of the side of the first electrode and on the spacer element.

19. The method of claim 16 , wherein the forming of the second electrode includes performing a chemical mechanical planarization (CMP) process.

Assignees

• Globalfoundries Sg Pte Ltd
• Globalfoundaries Singapore Pte Ltd

Inventors

• Loy Desmond Jia Jun
• Toh Eng Huat
• Tan Shyue Seng

Classifications

• H10N70/841

  Electrodes · CPC title

• H10N70/823 Primary

  adapted for essentially horizontal current flow, e.g. bridge type devices · CPC title

• H10N70/011

  Manufacture or treatment of multistable switching devices · CPC title

• H10N70/24

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10N70/245

  the species being metal cations, e.g. programmable metallization cells · CPC title