Capacitors in through glass vias

Patent metadata

Field	Value
Publication number	US-12349282-B2
Application number	US-202117482399-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Sep 22, 2021
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A capacitor comprising:
a glass layer with a first side and a second side opposite the first side;
a through glass via (TGV) that extends from the first side of the glass layer to the second side of the glass layer;
a first conductive layer on a wall of the TGV;
a dielectric layer on the first conductive layer within the TGV, wherein the dielectric layer has an end with a top surface at a same level as a top surface of an end of the first conductive layer; and
a second conductive layer on the dielectric layer within the TGV, wherein the first conductive layer and the second conductive layer are electrically isolated from each other.

2. The capacitor of claim 1 , wherein a shape of the TGV at the first side of the glass layer is a selected one of: a circle, an oval, or a rectangle.

3. The capacitor of claim 1 , wherein the TGV is a blind via.

4. The capacitor of claim 1 , wherein the TGV is a plurality of TGVs.

5. The capacitor of claim 4 , wherein the first conductive layer of a first TGV is electrically coupled with a first conductive layer of a second TGV; and wherein a second conductive layer of the first TGV is electrically coupled with a second conductive layer of the second TGV.

6. The capacitor of claim 1 , wherein the first conductive layer or the second conductive layer includes a selected one of: copper, iridium, oxygen, aluminum, or ruthenium.

7. The capacitor of claim 1 , wherein the dielectric layer includes a selected one of: titanium, hafnium, oxygen, or hertzium.

8. The capacitor of claim 1 , further comprising a buildup layer on the first side of the glass layer or the second side of the glass layer, the buildup layer includes one or more electrical trace that is electrically coupled with the first conductive layer or the second conductive layer.

9. A method comprising:
providing a glass layer having a first side and a second side opposite the first side;
forming a through glass via (TGV) in the glass layer, the TGV extending from the first side of the glass layer to the second side of the glass layer;
depositing a first layer of electrically conductive material on a wall of the TGV;
depositing a dielectric on the first layer of electrically conductive material, wherein the dielectric layer has an end with a top surface at a same level as a top surface of an end of the first conductive layer; and
depositing a second layer of electrically conductive material on the dielectric, wherein the first layer of conductive material and the second layer of conductive material are electrically isolated from each other.

10. The method of claim 9 , wherein depositing the first layer of electrically conductive material or depositing the second layer of electrically conductive material further includes depositing using an atomic layer deposition (ALD) process.

11. The method of claim 9 , wherein depositing the dielectric further includes depositing the dielectric using an ALD process.

12. The method of claim 9 , wherein the TGV has an aspect ratio of greater than 8 .

13. The method of claim 9 , wherein the dielectric is a first dielectric; and further comprising:
depositing a second dielectric on the second layer of electrically conductive material; and
depositing a third layer of electrically conductive material on the second dielectric, wherein the third layer of electrically conductive material is electrically isolated from the second layer of electrically conductive material, and wherein the first layer of electrically conductive material is electrically coupled with the third layer of electrically conductive material.

14. The method of claim 9 , further comprising:
forming a buildup layer on the first side of the glass layer, the buildup layer including a plurality of electrical traces, wherein at least one of the plurality of electrical traces is electrically coupled with the first layer of electrically conductive material.

15. The method of claim 14 , wherein the buildup layer is a first buildup layer and wherein the plurality of electrical traces is a first plurality of electrical traces; and further comprising:
forming a second buildup layer on the second side of the glass layer, the second buildup layer including a plurality of second electrical traces, wherein at least one of the plurality of second electrical traces is electrically coupled with the second layer of the electrically conductive material.

16. A package comprising:
a glass core with a first side and a second side opposite the first side, the glass core including:
a TGV that extends from the first side of the glass core to the second side of the glass core;
a first conductive layer on a wall of the TGV;
a dielectric layer on the first conductive layer within the TGV, wherein the dielectric layer has an end with a top surface at a same level as a top surface of an end of the first conductive layer; and
a second conductive layer on the dielectric layer within the TGV, wherein the first conductive layer and the second conductive layer are electrically isolated from each other; and

a redistribution layer (RDL) on the first side of the glass core, the RDL including an electrical routing electrically coupled with the first conductive layer.

17. The package of claim 16 , wherein the RDL is a first RDL, and further including a second RDL on the second side of the glass core, the second RDL including an electrical routing electrically coupled with the second conductive layer.

18. The package of claim 17 , wherein the first RDL is included in a first buildup layer and the second RDL is included in a second buildup layer.

19. The package of claim 16 , wherein the first conductive layer is electrically coupled with a Vdd and the second conductive layer is electrically coupled with a Vss.

20. The package of claim 16 , wherein the TGV is a plurality of TGVs.

21. The package of claim 20 , wherein the first conductive layer of a first TGV is electrically coupled with a first conductive layer of a second TGV; and wherein a second conductive layer of the first TGV is electrically coupled with a second conductive layer of the second TGV.

22. The package of claim 16 , wherein the first conductive layer or the second conductive layer includes a selected one of: copper, iridium, oxygen, aluminum, or ruthenium.

23. The package of claim 16 , wherein the dielectric layer includes a selected one of: titanium, hafnium, oxygen, or hertzium.

Assignees

• Intel Corp

Inventors

• Duong Benjamin
• Aleksov Aleksandar
• Castro De La Torre Helme A
• Darmawikarta Kristof
• Grujicic Darko
• Kandanur Sashi S
• Nad Suddhasattwa
• Pietambaram Srinivas V
• Shanmugam Rengarajan
• Sounart Thomas L
• Wall Marcel

Classifications

• H01G4/33 Primary

  Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

• H05K2201/09545

  Plated through-holes or blind vias without lands · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title

• H05K1/0306

  Inorganic insulating substrates, e.g. ceramic, glass · CPC title