Semiconductor package antenna structure and its manufacturing method

Patent metadata

Field	Value
Publication number	US-12347919-B2
Application number	US-202318519181-A
Country	US
Kind code	B2
Filing date	Nov 27, 2023
Priority date	Dec 9, 2022
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

The invention discloses a semiconductor package antenna structure and its manufacturing method, wherein the semiconductor package antenna structure includes a first substrate, a semiconductor chip, and a second substrate. The first substrate has at least two stacked first redistribution layers, and each of the first redistribution layers has a first dielectric layer, a first patterned metal layer, and/or a first conductive pillar layer. The semiconductor chip is embedded in the first substrate and coupled to the first redistribution layers. The second substrate has a second redistribution layer, a second conductive pillar layer, and an air dielectric layer, wherein the second conductive pillar layer is protruded from the second redistribution layer. The second substrate is connected to the first substrate by a second conductive pillar layer, and the air dielectric layer is located between the second redistribution layer, the second conductive pillar layer, and the first substrate.

First claim

What is claimed is:

1. A semiconductor package antenna structure, comprising:
a first substrate, which has at least two stacked first redistribution layers, and each of the first redistribution layers has a first dielectric layer, a first patterned metal layer, and/or a first conductive pillar layer;
a chip, which is embedded within the first substrate and is coupled to the first redistribution layers; and
a second substrate, which is disposed opposite to the first substrate and has a second redistribution layer, a second conductive pillar layer, and an air dielectric layer, wherein the second conductive pillar layer protrudes on the second redistribution layer;
wherein the second substrate is connected to the first substrate through the second conductive pillar layer, and the air dielectric layer is situated between the second redistribution layer, the second conductive pillar layer, and the first substrate and wherein an active surface of the chip faces away from the second substrate;
wherein a part of the first redistribution layer, a part of the second redistribution layer, and a part of the second conductive pillar layer form a transmitting antenna, while another part of the first redistribution layer, another part of the second redistribution layer, and another part of the second conductive pillar layer form a receiving antenna.

2. The semiconductor package antenna structure of claim 1 , wherein the first redistribution layer of the first substrate has a metal chip holder, which is in contact with the chip and is located between the chip and the second substrate.

3. The semiconductor package antenna structure of claim 1 , wherein the part of the first conductive pillar layer and the part of the second conductive pillar layer are used to adjust the radiation field pattern of the antenna.

4. The semiconductor package antenna structure of claim 1 wherein the second conductive pillar layer is a fence-like type or a continuous wall type, and the second conductive pillar layer encloses one or more spaces of the air dielectric layer.

5. The semiconductor package antenna structure of claim 2 , wherein the second conductive pillar layer is a fence-like type or a continuous wall type, and the second conductive pillar layer encloses one or more spaces of the air dielectric layer.

6. The semiconductor package antenna structure of claim 3 , wherein the second conductive pillar layer is a fence-like type or a continuous wall type, and the second conductive pillar layer encloses one or more spaces of the air dielectric layer.

7. A manufacturing method for the semiconductor package antenna structure, comprising the following steps:
forming a first substrate, which includes sequentially forming at least two layers of first redistribution layer, embedding a chip within these at least two layers of first redistribution layer during the process of forming at least two layers of the first redistribution layer, wherein an active surface of the chip is electrically coupled with one of the first redistribution layers;
forming a second substrate, which includes forming a second redistribution layer and forming a second conductive pillar layer protruding from the second redistribution layer, wherein the active surface of the chip faces away from the second substrate; and
bonding the first substrate with the second substrate, wherein the second conductive pillar layer is connected to the second substrate and an air dielectric layer is formed between the second redistribution layer, the second conductive pillar layer, and the first substrate;
wherein a part of the first redistribution layer, a part of the second redistribution layer, and a part of the second conductive pillar layer form a transmitting antenna, while another part of the first redistribution layer, another part of the second redistribution layer, and another part of the second conductive pillar layer form a receiving antenna.

8. The manufacturing method of claim 7 , wherein the second conductive pillar layer of the second substrate is connected to the first redistribution layer of the second substrate through the solder-ball, the conductive bump, or conductive adhesive.

9. The manufacturing method of claim 7 , wherein the step of forming at least two layers of first redistribution layer of the first substrate further comprising:
forming a second seed layer;
forming a photoresist layer with at least one second through hole on the second seed layer;
electroplating to form a first patterned metal layer and/or a first conductive pillar layer within the second through hole;
disposing the chip on the first patterned metal layer, wherein the active surface of the chip is coupled with another first redistribution layer;
removing the photoresist layer and the second seed layer; and
forming a first dielectric layer to cover the first patterned metal layer and/or the first conductive pillar layer, and the chip.

10. A manufacturing method for the semiconductor package antenna structure, comprising:
forming a first substrate, which includes sequentially forming at least two layers of first redistribution layer, embedding a chip within these at least two layers of first redistribution layer during the process of forming at least two layers of the first redistribution layer, wherein an active surface of the chip faces away from the second substrate, and it is electrically coupled with one of the first redistribution layers;
forming a second substrate on the first substrate that comprises:
forming a first seed layer on the first substrate;
forming a photoresist layer, which has at least one first through hole, on the first seed layer;
electroplating to form a second conductive pillar layer in the first through hole;
forming a second redistribution layer to connect to the second conductive pillar layer; and
removing the photoresist layer to form an air dielectric layer between the second redistribution layer, the second conductive pillar layer, and the first substrate; and

wherein the active surface of the chip faces away from the second substrate;
wherein a part of the first redistribution layer, a part of the second redistribution layer, and a part of the second conductive pillar layer form a transmitting antenna, while another part of the first redistribution layer, another part of the second redistribution layer, and another part of the second conductive pillar layer form a receiving antenna.

11. The manufacturing method of claim 10 , wherein the step of forming at least two layers of first redistribution layer of the first substrate further comprising:
forming a second seed layer;
forming a photoresist layer with at least one second through hole on the second seed layer;
electroplating to form a first patterned metal layer and/or a first conductive pillar layer within the second through hole;
disposing the chip on the first patterned metal layer, wherein the active surface of the chip is coupled with another first redistribution layer;
removing the photoresist layer and the second seed layer; and
forming a first dielectric layer to cover the first patterned metal layer and/or the first conductive pillar layer, and the chip.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Che-Wei
• Hsu Shih-Ping

Classifications

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title