Microelectronic assemblies with direct attach to circuit boards

Patent metadata

Field	Value
Publication number	US-12347782-B2
Application number	US-202117476301-A
Country	US
Kind code	B2
Filing date	Sep 15, 2021
Priority date	Sep 15, 2021
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a first redistribution layer (RDL), having a first surface, an opposing second surface, and first conductive pathways between the first and second surfaces, wherein the first surface of the first RDL includes first conductive contacts having a first pitch between 170 microns and 400 microns;
a first die in a first layer, wherein the first layer is on the second surface of the first RDL;
a conductive pillar in the first layer;
a second RDL on the first layer, the second RDL having a first surface, an opposing second surface, and second conductive pathways between the first and second surfaces, wherein the second surface of the second RDL includes second conductive contacts having a second pitch between 18 microns and 150 microns; and
a second die, in a second layer on the second RDL, wherein the second die is electrically coupled to the second conductive contacts and electrically coupled to the first conductive contacts via the first conductive pathways in the first RDL, the conductive pillar, the second conductive pathways in the second RDL, and the second conductive contacts.

2. The microelectronic assembly of claim 1 , wherein the first die has a first surface facing the first RDL and an opposing second surface, and the first die further includes:
third conductive contacts at the second surface, wherein the first die is electrically coupled to the second die via the third conductive contacts, the second conductive pathways in the second RDL, and the second conductive contacts.

3. The microelectronic assembly of claim 1 , wherein the conductive pillar is one of a plurality of conductive pillars having a third pitch between 75 microns and 150 microns.

4. The microelectronic assembly of claim 1 , further comprising:
a circuit board electrically coupled to the first conductive contacts.

5. The microelectronic assembly of claim 4 , wherein the circuit board is electrically coupled to the first conductive contacts by solder.

6. The microelectronic assembly of claim 1 , wherein the second die is one of a plurality of second dies.

7. The microelectronic assembly of claim 1 , wherein the first die is one of a plurality of first dies.

8. The microelectronic assembly of claim 1 , wherein the second die is electrically coupled to the second conductive contacts by solder.

9. The microelectronic assembly of claim 1 , wherein the first layer and the second layer include one or more insulating materials.

10. A microelectronic assembly, comprising:
a first redistribution layer (RDL), having a first surface, an opposing second surface, and first conductive pathways between the first and second surfaces, wherein the first surface of the first RDL includes first interconnects having a first pitch between 170 microns and 400 microns;
a first die, having a first surface and an opposing second surface, in a first layer, wherein the first layer is on the second surface of the first RDL;
a conductive pillar in the first layer;
a second RDL on the first layer; and
a second die, having a first surface and an opposing second surface, in a second layer, wherein the second layer is on the second RDL, wherein the first surface of the second die includes second interconnects having a second pitch between 18 microns and 150 microns, and wherein respective ones of the first interconnects are electrically coupled to respective ones of the second interconnects via the first conductive pathways in the first RDL, the conductive pillar, and the second conductive pathways in the second RDL.

11. The microelectronic assembly of claim 10 , wherein the second interconnects include solder.

12. The microelectronic assembly of claim 10 , wherein the first die further includes:
a plurality of third interconnects at the second surface, wherein respective ones of the third interconnects are electrically coupled to respective ones of the second interconnects via the second conductive pathways in the second RDL.

13. The microelectronic assembly of claim 10 , wherein the conductive pillar is one of a plurality of conductive pillars, the plurality of conductive pillars having a third pitch between 75 microns and 150 microns.

14. The microelectronic assembly of claim 10 , further comprising:
a circuit board electrically coupled to the first interconnects.

15. The microelectronic assembly of claim 14 , wherein the circuit board is a printed circuit board (PCB) or a mother board.

16. The microelectronic assembly of claim 14 , wherein the first interconnects include solder.

Assignees

• Intel Corp

Inventors

• Ganesan Sanka
• Lambert William J
• Penmecha Bharat Prasad
• Brun Xavier Francois

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title